| { |
| "area": 27.1728, |
| "cell_footprint": "sky130_fd_sc_lp__sdlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "dont_use": "true", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01226, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| "min_pulse_width_low": 0.63776, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
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| }, |
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| }, |
| { |
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| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
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| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
