commit | c530f5c8557df2b64da02b904902b6c7c4335b44 | [log] [tgz] |
---|---|---|
author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
tree | 5ddbe6c20a9f69f04e5651c440bd76b5530d8258 | |
parent | 5b95d7fa72b38163c9b5b96c131d35237c67ac38 [diff] |
verilog: Fixing usage of cell reserved word. `cell` is a Verilog reserved word. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>