Updates to spice, PEX and PXI files as well as the addition of lvs reports
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1.lvs.report b/cells/a21o/sky130_fd_sc_hvl__a21o_1.lvs.report
new file mode 100644
index 0000000..887607b
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__a21o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__a21o_1.sp ('sky130_fd_sc_hvl__a21o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/a21o/sky130_fd_sc_hvl__a21o_1.spice ('sky130_fd_sc_hvl__a21o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:03:06 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__a21o_1 sky130_fd_sc_hvl__a21o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__a21o_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__a21o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NHV)
+ 1 1 0 0 MP(PHV)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1.pex.spice b/cells/a21o/sky130_fd_sc_hvl__a21o_1.pex.spice
index 8c4d8d7..003dbcf 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1.pex.spice
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__a21o_1.pex.spice
-* Created: Fri Aug 28 09:32:08 2020
+* Created: Wed Sep 2 09:03:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1.pxi.spice b/cells/a21o/sky130_fd_sc_hvl__a21o_1.pxi.spice
index 6f9ab55..919a151 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__a21o_1.pxi.spice
-* Created: Fri Aug 28 09:32:08 2020
+* Created: Wed Sep 2 09:03:09 2020
*
x_PM_SKY130_FD_SC_HVL__A21O_1%VNB N_VNB_M1001_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__A21O_1%VNB
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1.spice b/cells/a21o/sky130_fd_sc_hvl__a21o_1.spice
index b05b660..1686756 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1.spice
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__a21o_1.spice
-* Created: Fri Aug 28 09:32:08 2020
+* Created: Wed Sep 2 09:03:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.lvs.report b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.lvs.report
new file mode 100644
index 0000000..7b30c1f
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__a21oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__a21oi_1.sp ('sky130_fd_sc_hvl__a21oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.spice ('sky130_fd_sc_hvl__a21oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:03:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__a21oi_1 sky130_fd_sc_hvl__a21oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__a21oi_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__a21oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.pex.spice b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.pex.spice
index 5cfb3c6..8b5b116 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__a21oi_1.pex.spice
-* Created: Fri Aug 28 09:32:15 2020
+* Created: Wed Sep 2 09:03:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.pxi.spice b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.pxi.spice
index 679e0f2..598b127 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__a21oi_1.pxi.spice
-* Created: Fri Aug 28 09:32:15 2020
+* Created: Wed Sep 2 09:03:16 2020
*
x_PM_SKY130_FD_SC_HVL__A21OI_1%VNB N_VNB_M1000_b VNB N_VNB_c_8_p VNB
+ PM_SKY130_FD_SC_HVL__A21OI_1%VNB
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.spice b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.spice
index 413602a..acfb998 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.spice
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__a21oi_1.spice
-* Created: Fri Aug 28 09:32:15 2020
+* Created: Wed Sep 2 09:03:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1.lvs.report b/cells/a22o/sky130_fd_sc_hvl__a22o_1.lvs.report
new file mode 100644
index 0000000..0f23b65
--- /dev/null
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__a22o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__a22o_1.sp ('sky130_fd_sc_hvl__a22o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/a22o/sky130_fd_sc_hvl__a22o_1.spice ('sky130_fd_sc_hvl__a22o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:03:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__a22o_1 sky130_fd_sc_hvl__a22o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__a22o_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__a22o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 1 1 0 0 MP(PHV)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1.pex.spice b/cells/a22o/sky130_fd_sc_hvl__a22o_1.pex.spice
index ff94004..9098944 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1.pex.spice
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__a22o_1.pex.spice
-* Created: Fri Aug 28 09:32:22 2020
+* Created: Wed Sep 2 09:03:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1.pxi.spice b/cells/a22o/sky130_fd_sc_hvl__a22o_1.pxi.spice
index 08283bb..b4f1165 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1.pxi.spice
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__a22o_1.pxi.spice
-* Created: Fri Aug 28 09:32:22 2020
+* Created: Wed Sep 2 09:03:23 2020
*
x_PM_SKY130_FD_SC_HVL__A22O_1%VNB N_VNB_M1008_b VNB N_VNB_c_4_p VNB
+ PM_SKY130_FD_SC_HVL__A22O_1%VNB
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1.spice b/cells/a22o/sky130_fd_sc_hvl__a22o_1.spice
index 4f9713e..66c54f1 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1.spice
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__a22o_1.spice
-* Created: Fri Aug 28 09:32:22 2020
+* Created: Wed Sep 2 09:03:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.lvs.report b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.lvs.report
new file mode 100644
index 0000000..5b60da6
--- /dev/null
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__a22oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__a22oi_1.sp ('sky130_fd_sc_hvl__a22oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.spice ('sky130_fd_sc_hvl__a22oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:03:27 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__a22oi_1 sky130_fd_sc_hvl__a22oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__a22oi_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__a22oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.pex.spice b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.pex.spice
index f9dbc8a..14dcfc3 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.pex.spice
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__a22oi_1.pex.spice
-* Created: Fri Aug 28 09:32:29 2020
+* Created: Wed Sep 2 09:03:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.pxi.spice b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.pxi.spice
index 4ad5923..1ee18b2 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.pxi.spice
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__a22oi_1.pxi.spice
-* Created: Fri Aug 28 09:32:29 2020
+* Created: Wed Sep 2 09:03:30 2020
*
x_PM_SKY130_FD_SC_HVL__A22OI_1%VNB N_VNB_M1003_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__A22OI_1%VNB
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.spice b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.spice
index 37e33e0..68cfb25 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.spice
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__a22oi_1.spice
-* Created: Fri Aug 28 09:32:29 2020
+* Created: Wed Sep 2 09:03:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1.lvs.report b/cells/and2/sky130_fd_sc_hvl__and2_1.lvs.report
new file mode 100644
index 0000000..777d33c
--- /dev/null
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__and2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__and2_1.sp ('sky130_fd_sc_hvl__and2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/and2/sky130_fd_sc_hvl__and2_1.spice ('sky130_fd_sc_hvl__and2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:03:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__and2_1 sky130_fd_sc_hvl__and2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__and2_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__and2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 3 3 0 0 MP(PHV)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1.pex.spice b/cells/and2/sky130_fd_sc_hvl__and2_1.pex.spice
index 9dd2a40..481aa0c 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1.pex.spice
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__and2_1.pex.spice
-* Created: Fri Aug 28 09:32:36 2020
+* Created: Wed Sep 2 09:03:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1.pxi.spice b/cells/and2/sky130_fd_sc_hvl__and2_1.pxi.spice
index ae335cb..4b48e5d 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1.pxi.spice
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__and2_1.pxi.spice
-* Created: Fri Aug 28 09:32:36 2020
+* Created: Wed Sep 2 09:03:37 2020
*
x_PM_SKY130_FD_SC_HVL__AND2_1%VNB N_VNB_M1005_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__AND2_1%VNB
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1.spice b/cells/and2/sky130_fd_sc_hvl__and2_1.spice
index 1cd2b18..c19e0e9 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1.spice
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__and2_1.spice
-* Created: Fri Aug 28 09:32:36 2020
+* Created: Wed Sep 2 09:03:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1.lvs.report b/cells/and3/sky130_fd_sc_hvl__and3_1.lvs.report
new file mode 100644
index 0000000..565cf95
--- /dev/null
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__and3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__and3_1.sp ('sky130_fd_sc_hvl__and3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/and3/sky130_fd_sc_hvl__and3_1.spice ('sky130_fd_sc_hvl__and3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:03:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__and3_1 sky130_fd_sc_hvl__and3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__and3_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__and3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 4 4 0 0 MP(PHV)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1.pex.spice b/cells/and3/sky130_fd_sc_hvl__and3_1.pex.spice
index 04100f8..4c7d7db 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1.pex.spice
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__and3_1.pex.spice
-* Created: Fri Aug 28 09:32:43 2020
+* Created: Wed Sep 2 09:03:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1.pxi.spice b/cells/and3/sky130_fd_sc_hvl__and3_1.pxi.spice
index e1872bf..1f5465c 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1.pxi.spice
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__and3_1.pxi.spice
-* Created: Fri Aug 28 09:32:43 2020
+* Created: Wed Sep 2 09:03:44 2020
*
x_PM_SKY130_FD_SC_HVL__AND3_1%VNB N_VNB_M1002_b VNB N_VNB_c_8_p VNB
+ PM_SKY130_FD_SC_HVL__AND3_1%VNB
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1.spice b/cells/and3/sky130_fd_sc_hvl__and3_1.spice
index 65fcc5e..845de3b 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1.spice
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__and3_1.spice
-* Created: Fri Aug 28 09:32:43 2020
+* Created: Wed Sep 2 09:03:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1.lvs.report b/cells/buf/sky130_fd_sc_hvl__buf_1.lvs.report
new file mode 100644
index 0000000..daf823b
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__buf_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__buf_1.sp ('sky130_fd_sc_hvl__buf_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/buf/sky130_fd_sc_hvl__buf_1.spice ('sky130_fd_sc_hvl__buf_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:03:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__buf_1 sky130_fd_sc_hvl__buf_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__buf_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__buf_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NHV)
+ 2 2 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1.pex.spice b/cells/buf/sky130_fd_sc_hvl__buf_1.pex.spice
index 18b1c2f..e2d323c 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1.pex.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_1.pex.spice
-* Created: Fri Aug 28 09:32:57 2020
+* Created: Wed Sep 2 09:03:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1.pxi.spice b/cells/buf/sky130_fd_sc_hvl__buf_1.pxi.spice
index fbdc2ca..f2f1419 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1.pxi.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_1.pxi.spice
-* Created: Fri Aug 28 09:32:57 2020
+* Created: Wed Sep 2 09:03:58 2020
*
x_PM_SKY130_FD_SC_HVL__BUF_1%VNB N_VNB_M1001_b VNB N_VNB_c_5_p VNB
+ PM_SKY130_FD_SC_HVL__BUF_1%VNB
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1.spice b/cells/buf/sky130_fd_sc_hvl__buf_1.spice
index 33f5eba..dc7b657 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_1.spice
-* Created: Fri Aug 28 09:32:57 2020
+* Created: Wed Sep 2 09:03:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16.lvs.report b/cells/buf/sky130_fd_sc_hvl__buf_16.lvs.report
new file mode 100644
index 0000000..71cb3f2
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__buf_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__buf_16.sp ('sky130_fd_sc_hvl__buf_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/buf/sky130_fd_sc_hvl__buf_16.spice ('sky130_fd_sc_hvl__buf_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:03:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__buf_16 sky130_fd_sc_hvl__buf_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__buf_16
+SOURCE CELL NAME: sky130_fd_sc_hvl__buf_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 22 22 MN (4 pins)
+ 22 22 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 45 44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NHV)
+ 2 2 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 44 layout mos transistors were reduced to 4.
+ 40 mos transistors were deleted by parallel reduction.
+ 44 source mos transistors were reduced to 4.
+ 40 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16.pex.spice b/cells/buf/sky130_fd_sc_hvl__buf_16.pex.spice
index a4bd3bc..1bc2b9d 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16.pex.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_16.pex.spice
-* Created: Fri Aug 28 09:32:50 2020
+* Created: Wed Sep 2 09:03:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16.pxi.spice b/cells/buf/sky130_fd_sc_hvl__buf_16.pxi.spice
index a7ce04a..7aad97b 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16.pxi.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_16.pxi.spice
-* Created: Fri Aug 28 09:32:50 2020
+* Created: Wed Sep 2 09:03:51 2020
*
x_PM_SKY130_FD_SC_HVL__BUF_16%VNB N_VNB_M1006_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__BUF_16%VNB
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16.spice b/cells/buf/sky130_fd_sc_hvl__buf_16.spice
index 9d693a0..71dbe6c 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_16.spice
-* Created: Fri Aug 28 09:32:50 2020
+* Created: Wed Sep 2 09:03:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2.lvs.report b/cells/buf/sky130_fd_sc_hvl__buf_2.lvs.report
new file mode 100644
index 0000000..ff17aac
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__buf_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__buf_2.sp ('sky130_fd_sc_hvl__buf_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/buf/sky130_fd_sc_hvl__buf_2.spice ('sky130_fd_sc_hvl__buf_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:04:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__buf_2 sky130_fd_sc_hvl__buf_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__buf_2
+SOURCE CELL NAME: sky130_fd_sc_hvl__buf_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NHV)
+ 2 2 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2.pex.spice b/cells/buf/sky130_fd_sc_hvl__buf_2.pex.spice
index 5e56a7d..59d413a 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2.pex.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_2.pex.spice
-* Created: Fri Aug 28 09:33:12 2020
+* Created: Wed Sep 2 09:04:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2.pxi.spice b/cells/buf/sky130_fd_sc_hvl__buf_2.pxi.spice
index 1aa65d2..47a4451 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2.pxi.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_2.pxi.spice
-* Created: Fri Aug 28 09:33:12 2020
+* Created: Wed Sep 2 09:04:05 2020
*
x_PM_SKY130_FD_SC_HVL__BUF_2%VNB N_VNB_M1002_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__BUF_2%VNB
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2.spice b/cells/buf/sky130_fd_sc_hvl__buf_2.spice
index 1034d34..f86cc2c 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_2.spice
-* Created: Fri Aug 28 09:33:12 2020
+* Created: Wed Sep 2 09:04:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32.lvs.report b/cells/buf/sky130_fd_sc_hvl__buf_32.lvs.report
new file mode 100644
index 0000000..e20d51a
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__buf_32.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__buf_32.sp ('sky130_fd_sc_hvl__buf_32')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/buf/sky130_fd_sc_hvl__buf_32.spice ('sky130_fd_sc_hvl__buf_32')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:04:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__buf_32 sky130_fd_sc_hvl__buf_32
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__buf_32
+SOURCE CELL NAME: sky130_fd_sc_hvl__buf_32
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 42 42 MN (4 pins)
+ 42 42 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 85 84
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NHV)
+ 2 2 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 84 layout mos transistors were reduced to 4.
+ 80 mos transistors were deleted by parallel reduction.
+ 84 source mos transistors were reduced to 4.
+ 80 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32.pex.spice b/cells/buf/sky130_fd_sc_hvl__buf_32.pex.spice
index 19aa13f..d9627b3 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32.pex.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_32.pex.spice
-* Created: Fri Aug 28 09:33:18 2020
+* Created: Wed Sep 2 09:04:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32.pxi.spice b/cells/buf/sky130_fd_sc_hvl__buf_32.pxi.spice
index 8013358..ba5dd14 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32.pxi.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_32.pxi.spice
-* Created: Fri Aug 28 09:33:18 2020
+* Created: Wed Sep 2 09:04:12 2020
*
x_PM_SKY130_FD_SC_HVL__BUF_32%VNB N_VNB_M1008_b VNB N_VNB_c_2_p VNB VNB
+ PM_SKY130_FD_SC_HVL__BUF_32%VNB
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32.spice b/cells/buf/sky130_fd_sc_hvl__buf_32.spice
index e196446..6c57a26 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_32.spice
-* Created: Fri Aug 28 09:33:18 2020
+* Created: Wed Sep 2 09:04:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4.lvs.report b/cells/buf/sky130_fd_sc_hvl__buf_4.lvs.report
new file mode 100644
index 0000000..f2008a2
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__buf_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__buf_4.sp ('sky130_fd_sc_hvl__buf_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/buf/sky130_fd_sc_hvl__buf_4.spice ('sky130_fd_sc_hvl__buf_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:04:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__buf_4 sky130_fd_sc_hvl__buf_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__buf_4
+SOURCE CELL NAME: sky130_fd_sc_hvl__buf_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NHV)
+ 2 2 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4.pex.spice b/cells/buf/sky130_fd_sc_hvl__buf_4.pex.spice
index 847f0ec..813e54d 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4.pex.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_4.pex.spice
-* Created: Fri Aug 28 09:33:25 2020
+* Created: Wed Sep 2 09:04:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4.pxi.spice b/cells/buf/sky130_fd_sc_hvl__buf_4.pxi.spice
index d1b2fd8..2e94764 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4.pxi.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_4.pxi.spice
-* Created: Fri Aug 28 09:33:25 2020
+* Created: Wed Sep 2 09:04:20 2020
*
x_PM_SKY130_FD_SC_HVL__BUF_4%VNB N_VNB_M1000_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__BUF_4%VNB
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4.spice b/cells/buf/sky130_fd_sc_hvl__buf_4.spice
index 1975934..a14b065 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_4.spice
-* Created: Fri Aug 28 09:33:25 2020
+* Created: Wed Sep 2 09:04:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8.lvs.report b/cells/buf/sky130_fd_sc_hvl__buf_8.lvs.report
new file mode 100644
index 0000000..cca591a
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__buf_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__buf_8.sp ('sky130_fd_sc_hvl__buf_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/buf/sky130_fd_sc_hvl__buf_8.spice ('sky130_fd_sc_hvl__buf_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:04:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__buf_8 sky130_fd_sc_hvl__buf_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__buf_8
+SOURCE CELL NAME: sky130_fd_sc_hvl__buf_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NHV)
+ 2 2 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 22 layout mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+ 22 source mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8.pex.spice b/cells/buf/sky130_fd_sc_hvl__buf_8.pex.spice
index 77330d5..af1a70e 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8.pex.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_8.pex.spice
-* Created: Fri Aug 28 09:33:32 2020
+* Created: Wed Sep 2 09:04:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8.pxi.spice b/cells/buf/sky130_fd_sc_hvl__buf_8.pxi.spice
index 6b72511..6fb8098 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8.pxi.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_8.pxi.spice
-* Created: Fri Aug 28 09:33:32 2020
+* Created: Wed Sep 2 09:04:27 2020
*
x_PM_SKY130_FD_SC_HVL__BUF_8%VNB N_VNB_M1003_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__BUF_8%VNB
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8.spice b/cells/buf/sky130_fd_sc_hvl__buf_8.spice
index 99501bf..0c1358c 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8.spice
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__buf_8.spice
-* Created: Fri Aug 28 09:33:32 2020
+* Created: Wed Sep 2 09:04:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1.lvs.report b/cells/conb/sky130_fd_sc_hvl__conb_1.lvs.report
new file mode 100644
index 0000000..17ee9bd
--- /dev/null
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__conb_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__conb_1.sp ('sky130_fd_sc_hvl__conb_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/conb/sky130_fd_sc_hvl__conb_1.spice ('sky130_fd_sc_hvl__conb_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:04:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__conb_1 sky130_fd_sc_hvl__conb_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__conb_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__conb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 2 2 R (2 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 2 2 R (2 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 2 2 0 0 R(SHORT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 2 passthrough layout nets were found.
+ 2 passthrough source nets were found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPB (port: VPB), VNB (port: VNB),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB HI VPWR VGND LO
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1.pex.spice b/cells/conb/sky130_fd_sc_hvl__conb_1.pex.spice
index 617e7c1..1cfc0fe 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1.pex.spice
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__conb_1.pex.spice
-* Created: Fri Aug 28 09:33:39 2020
+* Created: Wed Sep 2 09:04:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1.pxi.spice b/cells/conb/sky130_fd_sc_hvl__conb_1.pxi.spice
index b0a2113..27b4b3d 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1.pxi.spice
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__conb_1.pxi.spice
-* Created: Fri Aug 28 09:33:39 2020
+* Created: Wed Sep 2 09:04:34 2020
*
x_PM_SKY130_FD_SC_HVL__CONB_1%VNB N_VNB_X0_noxref_D0 VNB N_VNB_c_3_p VNB
+ PM_SKY130_FD_SC_HVL__CONB_1%VNB
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1.spice b/cells/conb/sky130_fd_sc_hvl__conb_1.spice
index b08aa10..128707a 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1.spice
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__conb_1.spice
-* Created: Fri Aug 28 09:33:39 2020
+* Created: Wed Sep 2 09:04:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4.lvs.report b/cells/decap/sky130_fd_sc_hvl__decap_4.lvs.report
new file mode 100644
index 0000000..fe2f680
--- /dev/null
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__decap_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__decap_4.sp ('sky130_fd_sc_hvl__decap_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/decap/sky130_fd_sc_hvl__decap_4.spice ('sky130_fd_sc_hvl__decap_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:04:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__decap_4 sky130_fd_sc_hvl__decap_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__decap_4
+SOURCE CELL NAME: sky130_fd_sc_hvl__decap_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 1 1 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4.pex.spice b/cells/decap/sky130_fd_sc_hvl__decap_4.pex.spice
index d1622cd..91f1225 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4.pex.spice
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__decap_4.pex.spice
-* Created: Fri Aug 28 09:33:45 2020
+* Created: Wed Sep 2 09:04:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4.pxi.spice b/cells/decap/sky130_fd_sc_hvl__decap_4.pxi.spice
index dd9a34a..c80faf9 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4.pxi.spice
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__decap_4.pxi.spice
-* Created: Fri Aug 28 09:33:45 2020
+* Created: Wed Sep 2 09:04:42 2020
*
x_PM_SKY130_FD_SC_HVL__DECAP_4%VNB N_VNB_M1000_b VNB N_VNB_c_4_p VNB
+ PM_SKY130_FD_SC_HVL__DECAP_4%VNB
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4.spice b/cells/decap/sky130_fd_sc_hvl__decap_4.spice
index 5ea93ed..562fdad 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4.spice
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__decap_4.spice
-* Created: Fri Aug 28 09:33:45 2020
+* Created: Wed Sep 2 09:04:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8.lvs.report b/cells/decap/sky130_fd_sc_hvl__decap_8.lvs.report
new file mode 100644
index 0000000..b0522cf
--- /dev/null
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__decap_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__decap_8.sp ('sky130_fd_sc_hvl__decap_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/decap/sky130_fd_sc_hvl__decap_8.spice ('sky130_fd_sc_hvl__decap_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:04:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__decap_8 sky130_fd_sc_hvl__decap_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__decap_8
+SOURCE CELL NAME: sky130_fd_sc_hvl__decap_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 1 1 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8.pex.spice b/cells/decap/sky130_fd_sc_hvl__decap_8.pex.spice
index 4bbf359..cbbccf3 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8.pex.spice
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__decap_8.pex.spice
-* Created: Fri Aug 28 09:33:52 2020
+* Created: Wed Sep 2 09:04:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8.pxi.spice b/cells/decap/sky130_fd_sc_hvl__decap_8.pxi.spice
index c4eceec..3900fa4 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8.pxi.spice
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__decap_8.pxi.spice
-* Created: Fri Aug 28 09:33:52 2020
+* Created: Wed Sep 2 09:04:49 2020
*
x_PM_SKY130_FD_SC_HVL__DECAP_8%VNB N_VNB_M1001_b VNB N_VNB_c_6_p VNB
+ PM_SKY130_FD_SC_HVL__DECAP_8%VNB
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8.spice b/cells/decap/sky130_fd_sc_hvl__decap_8.spice
index 3bac3db..88e6567 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8.spice
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__decap_8.spice
-* Created: Fri Aug 28 09:33:52 2020
+* Created: Wed Sep 2 09:04:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.lvs.report b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.lvs.report
new file mode 100644
index 0000000..792b719
--- /dev/null
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__dfrbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__dfrbp_1.sp ('sky130_fd_sc_hvl__dfrbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.spice ('sky130_fd_sc_hvl__dfrbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:04:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__dfrbp_1 sky130_fd_sc_hvl__dfrbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__dfrbp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__dfrbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 24 24
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 13 13 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 27 27
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NHV)
+ 13 13 0 0 MP(PHV)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 27 27 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK RESET_B D VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.pex.spice b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.pex.spice
index 457efe4..69ae5b0 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.pex.spice
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfrbp_1.pex.spice
-* Created: Fri Aug 28 09:33:59 2020
+* Created: Wed Sep 2 09:04:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.pxi.spice b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.pxi.spice
index ffcfc71..730c5b5 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.pxi.spice
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfrbp_1.pxi.spice
-* Created: Fri Aug 28 09:33:59 2020
+* Created: Wed Sep 2 09:04:58 2020
*
x_PM_SKY130_FD_SC_HVL__DFRBP_1%VNB N_VNB_M1020_b VNB N_VNB_c_2_p
+ PM_SKY130_FD_SC_HVL__DFRBP_1%VNB
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.spice b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.spice
index 787cc32..c4f84e1 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.spice
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfrbp_1.spice
-* Created: Fri Aug 28 09:33:59 2020
+* Created: Wed Sep 2 09:04:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.lvs.report b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.lvs.report
new file mode 100644
index 0000000..ef265bc
--- /dev/null
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__dfrtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__dfrtp_1.sp ('sky130_fd_sc_hvl__dfrtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.spice ('sky130_fd_sc_hvl__dfrtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:05:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__dfrtp_1 sky130_fd_sc_hvl__dfrtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__dfrtp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__dfrtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 23 23
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 12 12 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 25 25
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NHV)
+ 12 12 0 0 MP(PHV)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 25 25 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK RESET_B D VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.pex.spice b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.pex.spice
index 0c8c9a7..042d007 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.pex.spice
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfrtp_1.pex.spice
-* Created: Fri Aug 28 09:34:14 2020
+* Created: Wed Sep 2 09:05:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.pxi.spice b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.pxi.spice
index 32e82da..8e1f858 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.pxi.spice
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfrtp_1.pxi.spice
-* Created: Fri Aug 28 09:34:14 2020
+* Created: Wed Sep 2 09:05:05 2020
*
x_PM_SKY130_FD_SC_HVL__DFRTP_1%VNB N_VNB_M1016_b VNB N_VNB_c_3_p
+ PM_SKY130_FD_SC_HVL__DFRTP_1%VNB
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.spice b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.spice
index 96ea187..e000f16 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.spice
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfrtp_1.spice
-* Created: Fri Aug 28 09:34:14 2020
+* Created: Wed Sep 2 09:05:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.lvs.report b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.lvs.report
new file mode 100644
index 0000000..2c358a1
--- /dev/null
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__dfsbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__dfsbp_1.sp ('sky130_fd_sc_hvl__dfsbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.spice ('sky130_fd_sc_hvl__dfsbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:05:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__dfsbp_1 sky130_fd_sc_hvl__dfsbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__dfsbp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__dfsbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 25 25
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 11 11 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 26 26
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NHV)
+ 11 11 0 0 MP(PHV)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 26 26 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D SET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.pex.spice b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.pex.spice
index 4704669..31b0564 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.pex.spice
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfsbp_1.pex.spice
-* Created: Fri Aug 28 09:34:21 2020
+* Created: Wed Sep 2 09:05:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.pxi.spice b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.pxi.spice
index 117d83f..854092d 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.pxi.spice
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfsbp_1.pxi.spice
-* Created: Fri Aug 28 09:34:21 2020
+* Created: Wed Sep 2 09:05:12 2020
*
x_PM_SKY130_FD_SC_HVL__DFSBP_1%VNB N_VNB_M1023_b VNB N_VNB_c_2_p
+ PM_SKY130_FD_SC_HVL__DFSBP_1%VNB
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.spice b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.spice
index cebdf78..dc18f2a 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.spice
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfsbp_1.spice
-* Created: Fri Aug 28 09:34:21 2020
+* Created: Wed Sep 2 09:05:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.lvs.report b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.lvs.report
new file mode 100644
index 0000000..6b078af
--- /dev/null
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__dfstp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__dfstp_1.sp ('sky130_fd_sc_hvl__dfstp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.spice ('sky130_fd_sc_hvl__dfstp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:05:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__dfstp_1 sky130_fd_sc_hvl__dfstp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__dfstp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__dfstp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 24 24
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NHV)
+ 10 10 0 0 MP(PHV)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.pex.spice b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.pex.spice
index 801b1fa..b70ac42 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.pex.spice
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfstp_1.pex.spice
-* Created: Fri Aug 28 09:34:28 2020
+* Created: Wed Sep 2 09:05:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.pxi.spice b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.pxi.spice
index 26bb33d..b11bc7b 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.pxi.spice
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfstp_1.pxi.spice
-* Created: Fri Aug 28 09:34:28 2020
+* Created: Wed Sep 2 09:05:19 2020
*
x_PM_SKY130_FD_SC_HVL__DFSTP_1%VNB N_VNB_M1017_b VNB N_VNB_c_2_p
+ PM_SKY130_FD_SC_HVL__DFSTP_1%VNB
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.spice b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.spice
index 8e17a2f..5557952 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.spice
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfstp_1.spice
-* Created: Fri Aug 28 09:34:28 2020
+* Created: Wed Sep 2 09:05:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.lvs.report b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.lvs.report
new file mode 100644
index 0000000..ade4f05
--- /dev/null
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__dfxbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__dfxbp_1.sp ('sky130_fd_sc_hvl__dfxbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.spice ('sky130_fd_sc_hvl__dfxbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:05:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__dfxbp_1 sky130_fd_sc_hvl__dfxbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__dfxbp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__dfxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 20 20
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 10 10 0 0 MN(NHV)
+ 10 10 0 0 MP(PHV)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.pex.spice b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.pex.spice
index 41b7aac..ffdd4f1 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.pex.spice
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfxbp_1.pex.spice
-* Created: Fri Aug 28 09:34:35 2020
+* Created: Wed Sep 2 09:05:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.pxi.spice b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.pxi.spice
index 6ce4d3a..78bf1ab 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.pxi.spice
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfxbp_1.pxi.spice
-* Created: Fri Aug 28 09:34:35 2020
+* Created: Wed Sep 2 09:05:26 2020
*
x_PM_SKY130_FD_SC_HVL__DFXBP_1%VNB N_VNB_M1025_b VNB N_VNB_c_2_p
+ PM_SKY130_FD_SC_HVL__DFXBP_1%VNB
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.spice b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.spice
index a4b9f5a..e8ed39e 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.spice
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfxbp_1.spice
-* Created: Fri Aug 28 09:34:35 2020
+* Created: Wed Sep 2 09:05:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.lvs.report b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.lvs.report
new file mode 100644
index 0000000..ff065a2
--- /dev/null
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__dfxtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__dfxtp_1.sp ('sky130_fd_sc_hvl__dfxtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.spice ('sky130_fd_sc_hvl__dfxtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:05:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__dfxtp_1 sky130_fd_sc_hvl__dfxtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__dfxtp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__dfxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 18 18
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 14 14
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 20 20
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 8 8 0 0 MN(NHV)
+ 8 8 0 0 MP(PHV)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 20 20 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.pex.spice b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.pex.spice
index 675b7f2..9ea4fbd 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.pex.spice
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfxtp_1.pex.spice
-* Created: Fri Aug 28 09:34:42 2020
+* Created: Wed Sep 2 09:05:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.pxi.spice b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.pxi.spice
index 2f3489c..d090df4 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.pxi.spice
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfxtp_1.pxi.spice
-* Created: Fri Aug 28 09:34:42 2020
+* Created: Wed Sep 2 09:05:34 2020
*
x_PM_SKY130_FD_SC_HVL__DFXTP_1%VNB N_VNB_M1022_b VNB N_VNB_c_3_p VNB
+ PM_SKY130_FD_SC_HVL__DFXTP_1%VNB
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.spice b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.spice
index 6e752bf..29184e2 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.spice
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dfxtp_1.spice
-* Created: Fri Aug 28 09:34:42 2020
+* Created: Wed Sep 2 09:05:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2.lvs.report b/cells/diode/sky130_fd_sc_hvl__diode_2.lvs.report
new file mode 100644
index 0000000..4e4da2a
--- /dev/null
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2.lvs.report
@@ -0,0 +1,497 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__diode_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__diode_2.sp ('sky130_fd_sc_hvl__diode_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/diode/sky130_fd_sc_hvl__diode_2.spice ('sky130_fd_sc_hvl__diode_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:05:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of instances.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_hvl__diode_2 sky130_fd_sc_hvl__diode_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of instances (see below).
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__diode_2
+SOURCE CELL NAME: sky130_fd_sc_hvl__diode_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 5 5
+
+ Nets: 5 5
+
+ Instances: 0 1 * D (2 pins): p n
+ 1 0 * D (2 pins): p n
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 2 1
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 5 5
+
+ Nets: 5 5
+
+ Instances: 1 0 * D (2 pins): p n
+ ------ ------
+ Total Inst: 1 0
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT INSTANCES
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 D0(0.150,0.535) D(NDIODE_H) ** missing instance **
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 5 5 0 0
+
+ Nets: 5 5 0 0
+
+ Instances: 0 0 1 0 D(NDIODE_H)
+ ------- ------- --------- ---------
+ Total Inst: 0 0 1 0
+
+
+o Statistics:
+
+ 3 passthrough layout nets were found.
+ 5 passthrough source nets were found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+ 1 source instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR), VGND (port: VGND), VPB (port: VPB),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB DIODE VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2.pex.spice b/cells/diode/sky130_fd_sc_hvl__diode_2.pex.spice
index f1cf167..1370ee7 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2.pex.spice
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__diode_2.pex.spice
-* Created: Fri Aug 28 09:34:48 2020
+* Created: Wed Sep 2 09:05:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2.pxi.spice b/cells/diode/sky130_fd_sc_hvl__diode_2.pxi.spice
index 3ccc619..4f7a2a1 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2.pxi.spice
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__diode_2.pxi.spice
-* Created: Fri Aug 28 09:34:48 2020
+* Created: Wed Sep 2 09:05:41 2020
*
x_PM_SKY130_FD_SC_HVL__DIODE_2%VNB N_VNB_D0_noxref_pos VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__DIODE_2%VNB
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2.spice b/cells/diode/sky130_fd_sc_hvl__diode_2.spice
index 0e90ab9..bdf4e46 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2.spice
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__diode_2.spice
-* Created: Fri Aug 28 09:34:48 2020
+* Created: Wed Sep 2 09:05:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.lvs.report b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.lvs.report
new file mode 100644
index 0000000..f6a6054
--- /dev/null
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__dlclkp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__dlclkp_1.sp ('sky130_fd_sc_hvl__dlclkp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.spice ('sky130_fd_sc_hvl__dlclkp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:05:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__dlclkp_1 sky130_fd_sc_hvl__dlclkp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__dlclkp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__dlclkp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 17 17
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 4 4 0 0 MN(NHV)
+ 6 6 0 0 MP(PHV)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.pex.spice b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.pex.spice
index 1a05ef6..f01b503 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.pex.spice
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dlclkp_1.pex.spice
-* Created: Fri Aug 28 09:34:56 2020
+* Created: Wed Sep 2 09:05:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.pxi.spice b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.pxi.spice
index ad3732a..deffe1c 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.pxi.spice
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dlclkp_1.pxi.spice
-* Created: Fri Aug 28 09:34:56 2020
+* Created: Wed Sep 2 09:05:49 2020
*
x_PM_SKY130_FD_SC_HVL__DLCLKP_1%VNB N_VNB_M1002_b VNB N_VNB_c_3_p VNB
+ PM_SKY130_FD_SC_HVL__DLCLKP_1%VNB
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.spice b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.spice
index bb3a480..86fcbe9 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.spice
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dlclkp_1.spice
-* Created: Fri Aug 28 09:34:56 2020
+* Created: Wed Sep 2 09:05:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.lvs.report b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.lvs.report
new file mode 100644
index 0000000..e2d038a
--- /dev/null
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__dlrtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__dlrtp_1.sp ('sky130_fd_sc_hvl__dlrtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.spice ('sky130_fd_sc_hvl__dlrtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:05:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__dlrtp_1 sky130_fd_sc_hvl__dlrtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__dlrtp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__dlrtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 4 4 0 0 MN(NHV)
+ 6 6 0 0 MP(PHV)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.pex.spice b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.pex.spice
index de2627b..0753efa 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.pex.spice
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dlrtp_1.pex.spice
-* Created: Fri Aug 28 09:35:03 2020
+* Created: Wed Sep 2 09:05:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.pxi.spice b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.pxi.spice
index 908fe58..50e9dc6 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.pxi.spice
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dlrtp_1.pxi.spice
-* Created: Fri Aug 28 09:35:03 2020
+* Created: Wed Sep 2 09:05:56 2020
*
x_PM_SKY130_FD_SC_HVL__DLRTP_1%VNB N_VNB_M1019_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__DLRTP_1%VNB
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.spice b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.spice
index c1edaa1..00b3513 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.spice
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dlrtp_1.spice
-* Created: Fri Aug 28 09:35:03 2020
+* Created: Wed Sep 2 09:05:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.lvs.report b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.lvs.report
new file mode 100644
index 0000000..b6ab4c9
--- /dev/null
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__dlxtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__dlxtp_1.sp ('sky130_fd_sc_hvl__dlxtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.spice ('sky130_fd_sc_hvl__dlxtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:06:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__dlxtp_1 sky130_fd_sc_hvl__dlxtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__dlxtp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__dlxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 14 14
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 14 14
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 6 6 0 0 MN(NHV)
+ 6 6 0 0 MP(PHV)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 14 14 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE D VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.pex.spice b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.pex.spice
index 0cde3a2..10ae564 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.pex.spice
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dlxtp_1.pex.spice
-* Created: Fri Aug 28 09:35:18 2020
+* Created: Wed Sep 2 09:06:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.pxi.spice b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.pxi.spice
index f475563..1d6de17 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.pxi.spice
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dlxtp_1.pxi.spice
-* Created: Fri Aug 28 09:35:18 2020
+* Created: Wed Sep 2 09:06:03 2020
*
x_PM_SKY130_FD_SC_HVL__DLXTP_1%VNB N_VNB_M1010_b VNB N_VNB_c_3_p VNB
+ PM_SKY130_FD_SC_HVL__DLXTP_1%VNB
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.spice b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.spice
index 48bb2e5..31fd18c 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.spice
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__dlxtp_1.spice
-* Created: Fri Aug 28 09:35:18 2020
+* Created: Wed Sep 2 09:06:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1.lvs.report b/cells/einvn/sky130_fd_sc_hvl__einvn_1.lvs.report
new file mode 100644
index 0000000..e1865e9
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__einvn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__einvn_1.sp ('sky130_fd_sc_hvl__einvn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/einvn/sky130_fd_sc_hvl__einvn_1.spice ('sky130_fd_sc_hvl__einvn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:06:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__einvn_1 sky130_fd_sc_hvl__einvn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__einvn_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__einvn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 1 1 0 0 MP(PHV)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1.pex.spice b/cells/einvn/sky130_fd_sc_hvl__einvn_1.pex.spice
index e89aa6b..bb7a4ca 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1.pex.spice
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__einvn_1.pex.spice
-* Created: Fri Aug 28 09:35:25 2020
+* Created: Wed Sep 2 09:06:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1.pxi.spice b/cells/einvn/sky130_fd_sc_hvl__einvn_1.pxi.spice
index c14a966..4889fa8 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__einvn_1.pxi.spice
-* Created: Fri Aug 28 09:35:25 2020
+* Created: Wed Sep 2 09:06:11 2020
*
x_PM_SKY130_FD_SC_HVL__EINVN_1%VNB N_VNB_M1001_b VNB N_VNB_c_12_p VNB
+ PM_SKY130_FD_SC_HVL__EINVN_1%VNB
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1.spice b/cells/einvn/sky130_fd_sc_hvl__einvn_1.spice
index 296606f..cbdd5ea 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1.spice
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__einvn_1.spice
-* Created: Fri Aug 28 09:35:25 2020
+* Created: Wed Sep 2 09:06:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1.lvs.report b/cells/einvp/sky130_fd_sc_hvl__einvp_1.lvs.report
new file mode 100644
index 0000000..ac77ca6
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__einvp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__einvp_1.sp ('sky130_fd_sc_hvl__einvp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/einvp/sky130_fd_sc_hvl__einvp_1.spice ('sky130_fd_sc_hvl__einvp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:06:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__einvp_1 sky130_fd_sc_hvl__einvp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__einvp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__einvp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 1 1 0 0 MP(PHV)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1.pex.spice b/cells/einvp/sky130_fd_sc_hvl__einvp_1.pex.spice
index a294566..9a563d9 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1.pex.spice
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__einvp_1.pex.spice
-* Created: Fri Aug 28 09:35:32 2020
+* Created: Wed Sep 2 09:06:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1.pxi.spice b/cells/einvp/sky130_fd_sc_hvl__einvp_1.pxi.spice
index 4a55c61..7c83a71 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__einvp_1.pxi.spice
-* Created: Fri Aug 28 09:35:32 2020
+* Created: Wed Sep 2 09:06:18 2020
*
x_PM_SKY130_FD_SC_HVL__EINVP_1%VNB N_VNB_M1005_b VNB N_VNB_c_4_p VNB
+ PM_SKY130_FD_SC_HVL__EINVP_1%VNB
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1.spice b/cells/einvp/sky130_fd_sc_hvl__einvp_1.spice
index 828d10f..820b429 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1.spice
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__einvp_1.spice
-* Created: Fri Aug 28 09:35:32 2020
+* Created: Wed Sep 2 09:06:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fill/sky130_fd_sc_hvl__fill_1.lvs.report b/cells/fill/sky130_fd_sc_hvl__fill_1.lvs.report
new file mode 100644
index 0000000..93b4429
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_hvl__fill_1.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__fill_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__fill_1.sp ('sky130_fd_sc_hvl__fill_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/fill/sky130_fd_sc_hvl__fill_1.spice ('sky130_fd_sc_hvl__fill_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:06:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fill/sky130_fd_sc_hvl__fill_2.lvs.report b/cells/fill/sky130_fd_sc_hvl__fill_2.lvs.report
new file mode 100644
index 0000000..889bc4d
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_hvl__fill_2.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__fill_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__fill_2.sp ('sky130_fd_sc_hvl__fill_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/fill/sky130_fd_sc_hvl__fill_2.spice ('sky130_fd_sc_hvl__fill_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:06:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fill/sky130_fd_sc_hvl__fill_4.lvs.report b/cells/fill/sky130_fd_sc_hvl__fill_4.lvs.report
new file mode 100644
index 0000000..9cd5871
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_hvl__fill_4.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__fill_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__fill_4.sp ('sky130_fd_sc_hvl__fill_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/fill/sky130_fd_sc_hvl__fill_4.spice ('sky130_fd_sc_hvl__fill_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:06:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fill/sky130_fd_sc_hvl__fill_8.lvs.report b/cells/fill/sky130_fd_sc_hvl__fill_8.lvs.report
new file mode 100644
index 0000000..f03632e
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_hvl__fill_8.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__fill_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__fill_8.sp ('sky130_fd_sc_hvl__fill_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/fill/sky130_fd_sc_hvl__fill_8.spice ('sky130_fd_sc_hvl__fill_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:06:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1.lvs.report b/cells/inv/sky130_fd_sc_hvl__inv_1.lvs.report
new file mode 100644
index 0000000..a9434a4
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__inv_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__inv_1.sp ('sky130_fd_sc_hvl__inv_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/inv/sky130_fd_sc_hvl__inv_1.spice ('sky130_fd_sc_hvl__inv_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:06:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__inv_1 sky130_fd_sc_hvl__inv_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__inv_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__inv_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 1 1 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1.pex.spice b/cells/inv/sky130_fd_sc_hvl__inv_1.pex.spice
index ffbf256..ad695c9 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1.pex.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_1.pex.spice
-* Created: Fri Aug 28 09:35:59 2020
+* Created: Wed Sep 2 09:06:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1.pxi.spice b/cells/inv/sky130_fd_sc_hvl__inv_1.pxi.spice
index 0e56457..88939e1 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1.pxi.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_1.pxi.spice
-* Created: Fri Aug 28 09:35:59 2020
+* Created: Wed Sep 2 09:06:46 2020
*
x_PM_SKY130_FD_SC_HVL__INV_1%VNB N_VNB_M1001_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__INV_1%VNB
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1.spice b/cells/inv/sky130_fd_sc_hvl__inv_1.spice
index 1fc5d06..88569cf 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_1.spice
-* Created: Fri Aug 28 09:35:59 2020
+* Created: Wed Sep 2 09:06:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16.lvs.report b/cells/inv/sky130_fd_sc_hvl__inv_16.lvs.report
new file mode 100644
index 0000000..f517ce1
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__inv_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__inv_16.sp ('sky130_fd_sc_hvl__inv_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/inv/sky130_fd_sc_hvl__inv_16.spice ('sky130_fd_sc_hvl__inv_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:06:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__inv_16 sky130_fd_sc_hvl__inv_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__inv_16
+SOURCE CELL NAME: sky130_fd_sc_hvl__inv_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 1 1 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 2.
+ 30 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 2.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16.pex.spice b/cells/inv/sky130_fd_sc_hvl__inv_16.pex.spice
index 89f7ccd..afe60e6 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16.pex.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_16.pex.spice
-* Created: Fri Aug 28 09:35:52 2020
+* Created: Wed Sep 2 09:06:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16.pxi.spice b/cells/inv/sky130_fd_sc_hvl__inv_16.pxi.spice
index f066e35..740d5f4 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16.pxi.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_16.pxi.spice
-* Created: Fri Aug 28 09:35:52 2020
+* Created: Wed Sep 2 09:06:39 2020
*
x_PM_SKY130_FD_SC_HVL__INV_16%VNB N_VNB_M1002_b VNB N_VNB_c_2_p
+ PM_SKY130_FD_SC_HVL__INV_16%VNB
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16.spice b/cells/inv/sky130_fd_sc_hvl__inv_16.spice
index c998c29..7d6ba3e 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_16.spice
-* Created: Fri Aug 28 09:35:52 2020
+* Created: Wed Sep 2 09:06:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2.lvs.report b/cells/inv/sky130_fd_sc_hvl__inv_2.lvs.report
new file mode 100644
index 0000000..fd35d47
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__inv_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__inv_2.sp ('sky130_fd_sc_hvl__inv_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/inv/sky130_fd_sc_hvl__inv_2.spice ('sky130_fd_sc_hvl__inv_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:06:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__inv_2 sky130_fd_sc_hvl__inv_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__inv_2
+SOURCE CELL NAME: sky130_fd_sc_hvl__inv_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 1 1 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2.pex.spice b/cells/inv/sky130_fd_sc_hvl__inv_2.pex.spice
index 1959198..9f31f84 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2.pex.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_2.pex.spice
-* Created: Fri Aug 28 09:36:06 2020
+* Created: Wed Sep 2 09:06:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2.pxi.spice b/cells/inv/sky130_fd_sc_hvl__inv_2.pxi.spice
index d9c2646..684d091 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2.pxi.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_2.pxi.spice
-* Created: Fri Aug 28 09:36:06 2020
+* Created: Wed Sep 2 09:06:53 2020
*
x_PM_SKY130_FD_SC_HVL__INV_2%VNB N_VNB_M1001_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__INV_2%VNB
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2.spice b/cells/inv/sky130_fd_sc_hvl__inv_2.spice
index 8379c0e..d8b7580 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_2.spice
-* Created: Fri Aug 28 09:36:06 2020
+* Created: Wed Sep 2 09:06:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4.lvs.report b/cells/inv/sky130_fd_sc_hvl__inv_4.lvs.report
new file mode 100644
index 0000000..f133e01
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__inv_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__inv_4.sp ('sky130_fd_sc_hvl__inv_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/inv/sky130_fd_sc_hvl__inv_4.spice ('sky130_fd_sc_hvl__inv_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:06:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__inv_4 sky130_fd_sc_hvl__inv_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__inv_4
+SOURCE CELL NAME: sky130_fd_sc_hvl__inv_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 1 1 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4.pex.spice b/cells/inv/sky130_fd_sc_hvl__inv_4.pex.spice
index 3fee03a..d658aa4 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4.pex.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_4.pex.spice
-* Created: Fri Aug 28 09:36:21 2020
+* Created: Wed Sep 2 09:07:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4.pxi.spice b/cells/inv/sky130_fd_sc_hvl__inv_4.pxi.spice
index 8963d9e..eff2c18 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4.pxi.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_4.pxi.spice
-* Created: Fri Aug 28 09:36:21 2020
+* Created: Wed Sep 2 09:07:00 2020
*
x_PM_SKY130_FD_SC_HVL__INV_4%VNB N_VNB_M1001_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__INV_4%VNB
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4.spice b/cells/inv/sky130_fd_sc_hvl__inv_4.spice
index a94c1e7..0144369 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_4.spice
-* Created: Fri Aug 28 09:36:21 2020
+* Created: Wed Sep 2 09:07:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8.lvs.report b/cells/inv/sky130_fd_sc_hvl__inv_8.lvs.report
new file mode 100644
index 0000000..1a24c50
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__inv_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__inv_8.sp ('sky130_fd_sc_hvl__inv_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/inv/sky130_fd_sc_hvl__inv_8.spice ('sky130_fd_sc_hvl__inv_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:07:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__inv_8 sky130_fd_sc_hvl__inv_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__inv_8
+SOURCE CELL NAME: sky130_fd_sc_hvl__inv_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 1 1 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 2.
+ 14 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 2.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8.pex.spice b/cells/inv/sky130_fd_sc_hvl__inv_8.pex.spice
index 8f816a7..f56e53a 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8.pex.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_8.pex.spice
-* Created: Fri Aug 28 09:36:29 2020
+* Created: Wed Sep 2 09:07:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8.pxi.spice b/cells/inv/sky130_fd_sc_hvl__inv_8.pxi.spice
index 56c93d6..aed45c9 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8.pxi.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_8.pxi.spice
-* Created: Fri Aug 28 09:36:29 2020
+* Created: Wed Sep 2 09:07:07 2020
*
x_PM_SKY130_FD_SC_HVL__INV_8%VNB N_VNB_M1000_b VNB N_VNB_c_14_p VNB
+ PM_SKY130_FD_SC_HVL__INV_8%VNB
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8.spice b/cells/inv/sky130_fd_sc_hvl__inv_8.spice
index 888a6e8..4ff0269 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8.spice
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__inv_8.spice
-* Created: Fri Aug 28 09:36:29 2020
+* Created: Wed Sep 2 09:07:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.lvs.report b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.lvs.report
new file mode 100644
index 0000000..8fd13d2
--- /dev/null
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.lvs.report
@@ -0,0 +1,512 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__lsbufhv2hv_hl_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.sp ('sky130_fd_sc_hvl__lsbufhv2hv_hl_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.spice ('sky130_fd_sc_hvl__lsbufhv2hv_hl_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:07:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of instances.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_hvl__lsbufhv2hv_hl_1 sky130_fd_sc_hvl__lsbufhv2hv_hl_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of instances (see below).
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__lsbufhv2hv_hl_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__lsbufhv2hv_hl_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 9 *
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 3 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 0 * MN (4 pins)
+ 2 2 MP (4 pins)
+ 0 1 * SMN2 (4 pins)
+ ------ ------
+ Total Inst: 4 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT INSTANCES
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 M0(3.310,0.535) MN(NHV) ** missing instance **
+
+--------------------------------------------------------------------------------------------------------------
+
+ 2 M1(4.310,0.535) MN(NHV) ** missing instance **
+
+--------------------------------------------------------------------------------------------------------------
+
+ 3 ** missing gate ** (SMN2)
+
+ Transistors:
+ M1000 MN(NHV)
+ M1002 MN(NHV)
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 0 0 2 0 MN(NHV)
+ 2 2 0 0 MP(PHV)
+ 0 0 0 1 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 2 1
+
+
+o Statistics:
+
+ 2 passthrough layout nets were found.
+ 3 passthrough source nets were found.
+
+ 3 layout instances were filtered and their pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR), VPB (port: VPB),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB LOWHVPWR A X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.pex.spice b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.pex.spice
index 85bc06c..9789638 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.pex.spice
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbufhv2hv_hl_1.pex.spice
-* Created: Fri Aug 28 09:36:36 2020
+* Created: Wed Sep 2 09:07:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.pxi.spice b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.pxi.spice
index 10f0ec6..c39bc9c 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.pxi.spice
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbufhv2hv_hl_1.pxi.spice
-* Created: Fri Aug 28 09:36:36 2020
+* Created: Wed Sep 2 09:07:14 2020
*
x_PM_SKY130_FD_SC_HVL__LSBUFHV2HV_HL_1%VNB N_VNB_M0_noxref_b VNB VNB N_VNB_c_7_p
+ VNB PM_SKY130_FD_SC_HVL__LSBUFHV2HV_HL_1%VNB
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.spice b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.spice
index 6dec123..d4038f2 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.spice
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbufhv2hv_hl_1.spice
-* Created: Fri Aug 28 09:36:36 2020
+* Created: Wed Sep 2 09:07:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.lvs.report b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.lvs.report
new file mode 100644
index 0000000..a964194
--- /dev/null
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.lvs.report
@@ -0,0 +1,503 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__lsbufhv2hv_lh_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.sp ('sky130_fd_sc_hvl__lsbufhv2hv_lh_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.spice ('sky130_fd_sc_hvl__lsbufhv2hv_lh_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:07:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets.
+ Error: Connectivity errors.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_hvl__lsbufhv2hv_lh_1 sky130_fd_sc_hvl__lsbufhv2hv_lh_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets (see below).
+ Error: Connectivity errors.
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__lsbufhv2hv_lh_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__lsbufhv2hv_lh_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 13 *
+
+ Instances: 11 11 MN (4 pins)
+ 5 5 MP (4 pins)
+ 3 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 13 *
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT NETS
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 Net VPWR VPWR
+ a_1793_563#
+ --- 4 Connections On This Net --- --- 4 Connections On This Net ---
+
+--------------------------------------------------------------------------------------------------------------
+
+ 2 Net VGND VGND
+ a_779_141#
+ --- 6 Connections On This Net --- --- 6 Connections On This Net ---
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 11 13 0 0
+
+ Instances: 5 5 0 0 MN(NHV)
+ 5 5 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 3 layout instances were filtered and their pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB LOWHVPWR A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.pex.spice b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.pex.spice
index 85fcfef..223ed50 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.pex.spice
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbufhv2hv_lh_1.pex.spice
-* Created: Fri Aug 28 09:36:43 2020
+* Created: Wed Sep 2 09:07:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.pxi.spice b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.pxi.spice
index 9d0aba1..ca6c7d9 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.pxi.spice
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbufhv2hv_lh_1.pxi.spice
-* Created: Fri Aug 28 09:36:43 2020
+* Created: Wed Sep 2 09:07:21 2020
*
x_PM_SKY130_FD_SC_HVL__LSBUFHV2HV_LH_1%VNB N_VNB_M1011_b VNB VNB N_VNB_c_6_p
+ N_VNB_c_38_p VNB VNB PM_SKY130_FD_SC_HVL__LSBUFHV2HV_LH_1%VNB
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.spice b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.spice
index 01c9159..eadf533 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.spice
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbufhv2hv_lh_1.spice
-* Created: Fri Aug 28 09:36:43 2020
+* Created: Wed Sep 2 09:07:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.lvs.report b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.lvs.report
new file mode 100644
index 0000000..bc06dca
--- /dev/null
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.lvs.report
@@ -0,0 +1,505 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__lsbufhv2lv_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__lsbufhv2lv_1.sp ('sky130_fd_sc_hvl__lsbufhv2lv_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.spice ('sky130_fd_sc_hvl__lsbufhv2lv_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:07:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets.
+ Error: Connectivity errors.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_hvl__lsbufhv2lv_1 sky130_fd_sc_hvl__lsbufhv2lv_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets (see below).
+ Error: Connectivity errors.
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__lsbufhv2lv_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__lsbufhv2lv_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 13 *
+
+ Instances: 11 11 MN (4 pins)
+ 5 5 MP (4 pins)
+ 3 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 13 *
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT NETS
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 Net VPWR VPWR
+ a_30_443#
+ --- 3 Connections On This Net --- --- 3 Connections On This Net ---
+
+--------------------------------------------------------------------------------------------------------------
+
+ 2 Net VGND VGND
+ a_187_207#
+ --- 6 Connections On This Net --- --- 6 Connections On This Net ---
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 11 13 0 0
+
+ Instances: 4 4 0 0 MN(NHV)
+ 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 2 2 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 3 layout instances were filtered and their pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB LVPWR A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.pex.spice b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.pex.spice
index e1bc711..77a7160 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.pex.spice
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbufhv2lv_1.pex.spice
-* Created: Fri Aug 28 09:36:50 2020
+* Created: Wed Sep 2 09:07:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.pxi.spice b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.pxi.spice
index 904c976..4ec2ecb 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.pxi.spice
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbufhv2lv_1.pxi.spice
-* Created: Fri Aug 28 09:36:50 2020
+* Created: Wed Sep 2 09:07:28 2020
*
x_PM_SKY130_FD_SC_HVL__LSBUFHV2LV_1%VNB N_VNB_M1011_b VNB VNB N_VNB_c_24_p
+ N_VNB_c_5_p VNB VNB PM_SKY130_FD_SC_HVL__LSBUFHV2LV_1%VNB
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.spice b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.spice
index e01b336..a897cb2 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.spice
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbufhv2lv_1.spice
-* Created: Fri Aug 28 09:36:50 2020
+* Created: Wed Sep 2 09:07:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.lvs.report b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.lvs.report
new file mode 100644
index 0000000..77a01d8
--- /dev/null
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.lvs.report
@@ -0,0 +1,512 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__lsbufhv2lv_simple_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.sp ('sky130_fd_sc_hvl__lsbufhv2lv_simple_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.spice ('sky130_fd_sc_hvl__lsbufhv2lv_simple_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:07:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of instances.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_hvl__lsbufhv2lv_simple_1 sky130_fd_sc_hvl__lsbufhv2lv_simple_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of instances (see below).
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__lsbufhv2lv_simple_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__lsbufhv2lv_simple_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 9 *
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 3 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 0 * MN (4 pins)
+ 2 2 MP (4 pins)
+ 0 1 * SMN2 (4 pins)
+ ------ ------
+ Total Inst: 4 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT INSTANCES
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 M0(3.310,0.535) MN(NHV) ** missing instance **
+
+--------------------------------------------------------------------------------------------------------------
+
+ 2 M1(4.310,0.535) MN(NHV) ** missing instance **
+
+--------------------------------------------------------------------------------------------------------------
+
+ 3 ** missing gate ** (SMN2)
+
+ Transistors:
+ M1000 MN(NHV)
+ M1002 MN(NHV)
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 0 0 2 0 MN(NHV)
+ 2 2 0 0 MP(PHV)
+ 0 0 0 1 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 2 1
+
+
+o Statistics:
+
+ 2 passthrough layout nets were found.
+ 3 passthrough source nets were found.
+
+ 3 layout instances were filtered and their pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR), VPB (port: VPB),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB LVPWR A X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.pex.spice b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.pex.spice
index 987429c..498db20 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.pex.spice
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbufhv2lv_simple_1.pex.spice
-* Created: Fri Aug 28 09:36:57 2020
+* Created: Wed Sep 2 09:07:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.pxi.spice b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.pxi.spice
index 59bdcef..e76945f 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.pxi.spice
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbufhv2lv_simple_1.pxi.spice
-* Created: Fri Aug 28 09:36:57 2020
+* Created: Wed Sep 2 09:07:35 2020
*
x_PM_SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_1%VNB N_VNB_M0_noxref_b VNB VNB
+ N_VNB_c_9_p VNB PM_SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_1%VNB
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.spice b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.spice
index f0991f1..f5e1759 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.spice
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbufhv2lv_simple_1.spice
-* Created: Fri Aug 28 09:36:57 2020
+* Created: Wed Sep 2 09:07:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.lvs.report b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.lvs.report
new file mode 100644
index 0000000..3ad94ab
--- /dev/null
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.lvs.report
@@ -0,0 +1,505 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__lsbuflv2hv_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__lsbuflv2hv_1.sp ('sky130_fd_sc_hvl__lsbuflv2hv_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.spice ('sky130_fd_sc_hvl__lsbuflv2hv_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:07:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets.
+ Error: Connectivity errors.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_hvl__lsbuflv2hv_1 sky130_fd_sc_hvl__lsbuflv2hv_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets (see below).
+ Error: Connectivity errors.
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__lsbuflv2hv_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__lsbuflv2hv_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 14 *
+
+ Instances: 14 14 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 14 *
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT NETS
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 Net VPWR VPWR
+ a_1606_563#
+ --- 5 Connections On This Net --- --- 5 Connections On This Net ---
+
+--------------------------------------------------------------------------------------------------------------
+
+ 2 Net VGND VGND
+ a_686_151#
+ --- 7 Connections On This Net --- --- 7 Connections On This Net ---
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 14 0 0
+
+ Instances: 4 4 0 0 MN(NHV)
+ 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 4 4 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 3 layout instances were filtered and their pins removed from adjoining nets.
+
+ 10 layout mos transistors were reduced to 2.
+ 8 mos transistors were deleted by parallel reduction.
+ 10 source mos transistors were reduced to 2.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB LVPWR A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.pex.spice b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.pex.spice
index ff14ac0..64bbc1e 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.pex.spice
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbuflv2hv_1.pex.spice
-* Created: Fri Aug 28 09:37:04 2020
+* Created: Wed Sep 2 09:07:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.pxi.spice b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.pxi.spice
index 30c4da8..77fb764 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.pxi.spice
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbuflv2hv_1.pxi.spice
-* Created: Fri Aug 28 09:37:04 2020
+* Created: Wed Sep 2 09:07:42 2020
*
x_PM_SKY130_FD_SC_HVL__LSBUFLV2HV_1%VNB N_VNB_M1014_b VNB VNB N_VNB_c_25_p
+ N_VNB_c_15_p VNB VNB PM_SKY130_FD_SC_HVL__LSBUFLV2HV_1%VNB
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.spice b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.spice
index 2a5119d..88e18c0 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.spice
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbuflv2hv_1.spice
-* Created: Fri Aug 28 09:37:04 2020
+* Created: Wed Sep 2 09:07:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.lvs.report b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.lvs.report
new file mode 100644
index 0000000..28f23f0
--- /dev/null
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.lvs.report
@@ -0,0 +1,525 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.sp ('sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.spice ('sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:07:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets.
+ Error: Different numbers of instances.
+ Error: Connectivity errors.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3 sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets (see below).
+ Error: Different numbers of instances (see below).
+ Error: Connectivity errors.
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3
+SOURCE CELL NAME: sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 18 *
+
+ Instances: 26 26 MN (4 pins)
+ 22 22 MP (4 pins)
+ 2 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 50 48
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 17 *
+
+ Instances: 10 10 MN (4 pins)
+ 9 7 * MP (4 pins)
+ 0 1 * SMP2 (4 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT NETS
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 Net VGND VGND
+ a_362_133#
+ --- 12 Connections On This Net --- --- 12 Connections On This Net ---
+
+
+**************************************************************************************************************
+ INCORRECT INSTANCES
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 2 M39(4.200,2.425) MP(PHV) ** missing instance **
+
+--------------------------------------------------------------------------------------------------------------
+
+ 3 M43(10.460,2.035) MP(PHV) ** missing instance **
+
+--------------------------------------------------------------------------------------------------------------
+
+ 4 ** missing gate ** (SMP2)
+
+ Transistors:
+ M1021 MP(PHV)
+ M1017 MP(PHV)
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 17 0 0
+
+ Instances: 5 5 0 0 MN(NHV)
+ 2 2 0 0 MN(NHVNATIVE)
+ 3 3 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 4 4 2 0 MP(PHV)
+ 0 0 0 1 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 17 17 2 1
+
+
+o Statistics:
+
+ 2 layout instances were filtered and their pins removed from adjoining nets.
+
+ 42 layout mos transistors were reduced to 13.
+ 29 mos transistors were deleted by parallel reduction.
+ 42 source mos transistors were reduced to 13.
+ 29 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB LVPWR VGND SLEEP_B A X VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.pex.spice b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.pex.spice
index 1189963..7b8e84a 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.pex.spice
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.pex.spice
-* Created: Fri Aug 28 09:37:12 2020
+* Created: Wed Sep 2 09:07:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.pxi.spice b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.pxi.spice
index a35dea2..faaa481 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.pxi.spice
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.pxi.spice
-* Created: Fri Aug 28 09:37:12 2020
+* Created: Wed Sep 2 09:07:49 2020
*
x_PM_SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_3%VNB N_VNB_M1018_b VNB VNB
+ N_VNB_c_10_p N_VNB_c_6_p VNB VNB
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.spice b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.spice
index fded0d7..5af6ff1 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.spice
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.spice
-* Created: Fri Aug 28 09:37:12 2020
+* Created: Wed Sep 2 09:07:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.lvs.report b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.lvs.report
new file mode 100644
index 0000000..e14124d
--- /dev/null
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.lvs.report
@@ -0,0 +1,507 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.sp ('sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.spice ('sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:07:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets.
+ Error: Connectivity errors.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1 sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets (see below).
+ Error: Connectivity errors.
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 16 *
+
+ Instances: 11 11 MN (4 pins)
+ 6 6 MP (4 pins)
+ 2 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 17
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 16 *
+
+ Instances: 8 8 MN (4 pins)
+ 6 6 MP (4 pins)
+ ------ ------
+ Total Inst: 14 14
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT NETS
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 Net VPWR VPWR
+ a_341_485#
+ --- 5 Connections On This Net --- --- 5 Connections On This Net ---
+
+--------------------------------------------------------------------------------------------------------------
+
+ 2 Net VGND VGND
+ a_341_183#
+ --- 7 Connections On This Net --- --- 7 Connections On This Net ---
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 16 0 0
+
+ Instances: 6 6 0 0 MN(NHV)
+ 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 4 4 0 0 MP(PHV)
+ ------- ------- --------- ---------
+ Total Inst: 14 14 0 0
+
+
+o Statistics:
+
+ 1 passthrough source net was found.
+
+ 2 layout instances were filtered and their pins removed from adjoining nets.
+
+ 6 layout mos transistors were reduced to 3.
+ 3 mos transistors were deleted by parallel reduction.
+ 6 source mos transistors were reduced to 3.
+ 3 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB LVPWR SLEEP_B A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.pex.spice b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.pex.spice
index 67d56c9..35957fb 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.pex.spice
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.pex.spice
-* Created: Fri Aug 28 09:37:27 2020
+* Created: Wed Sep 2 09:07:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.pxi.spice b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.pxi.spice
index bd45a87..794be53 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.pxi.spice
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.pxi.spice
-* Created: Fri Aug 28 09:37:27 2020
+* Created: Wed Sep 2 09:07:56 2020
*
x_PM_SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_1%VNB N_VNB_M1009_b VNB VNB
+ N_VNB_c_8_p N_VNB_c_50_p VNB VNB
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.spice b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.spice
index 6731d28..0dfae64 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.spice
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.spice
-* Created: Fri Aug 28 09:37:27 2020
+* Created: Wed Sep 2 09:07:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.lvs.report b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.lvs.report
new file mode 100644
index 0000000..2b4a937
--- /dev/null
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.lvs.report
@@ -0,0 +1,531 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.sp ('sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.spice ('sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:08:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets.
+ Error: Different numbers of instances.
+ Error: Connectivity errors.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1 sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets (see below).
+ Error: Different numbers of instances (see below).
+ Error: Connectivity errors.
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 13 15 *
+
+ Instances: 10 10 MN (4 pins)
+ 9 9 MP (4 pins)
+ 3 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 22 19
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 13 *
+
+ Instances: 5 5 MN (4 pins)
+ 8 5 * MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 0 1 * SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 14 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT NETS
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 Net VGND VGND
+ a_686_151#
+ --- 7 Connections On This Net --- --- 7 Connections On This Net ---
+
+
+**************************************************************************************************************
+ INCORRECT INSTANCES
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 2 M15(8.470,2.815) MP(PHV) ** missing instance **
+
+--------------------------------------------------------------------------------------------------------------
+
+ 3 M17(9.910,2.815) MP(PHV) ** missing instance **
+
+--------------------------------------------------------------------------------------------------------------
+
+ 4 M13(7.030,2.815) MP(PHV) ** missing instance **
+
+--------------------------------------------------------------------------------------------------------------
+
+ 5 ** missing gate ** (SPMP_2_1)
+
+ Transistors:
+ M1003 MP(PHV)
+ M1002 MP(PHV)
+ M1006 MP(PHV)
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 13 0 0
+
+ Instances: 3 3 0 0 MN(NHV)
+ 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 3 3 3 0 MP(PHV)
+ 1 1 0 0 SMN2
+ 0 0 0 1 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 11 11 3 1
+
+
+o Statistics:
+
+ 3 layout instances were filtered and their pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB LVPWR A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.pex.spice b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.pex.spice
index a0bc340..1bb6806 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.pex.spice
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.pex.spice
-* Created: Fri Aug 28 09:37:35 2020
+* Created: Wed Sep 2 09:08:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.pxi.spice b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.pxi.spice
index 80f1060..14bc58e 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.pxi.spice
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.pxi.spice
-* Created: Fri Aug 28 09:37:35 2020
+* Created: Wed Sep 2 09:08:03 2020
*
x_PM_SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_1%VNB N_VNB_M1015_b VNB VNB
+ N_VNB_c_62_p VNB VNB PM_SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_1%VNB
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.spice b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.spice
index 1dda896..1cc21c2 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.spice
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.spice
-* Created: Fri Aug 28 09:37:35 2020
+* Created: Wed Sep 2 09:08:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1.lvs.report b/cells/mux2/sky130_fd_sc_hvl__mux2_1.lvs.report
new file mode 100644
index 0000000..3a4b8f7
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__mux2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__mux2_1.sp ('sky130_fd_sc_hvl__mux2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/mux2/sky130_fd_sc_hvl__mux2_1.spice ('sky130_fd_sc_hvl__mux2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:08:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__mux2_1 sky130_fd_sc_hvl__mux2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__mux2_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__mux2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NHV)
+ 2 2 0 0 MP(PHV)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S A0 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1.pex.spice b/cells/mux2/sky130_fd_sc_hvl__mux2_1.pex.spice
index c57ae64..7700269 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1.pex.spice
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__mux2_1.pex.spice
-* Created: Fri Aug 28 09:37:42 2020
+* Created: Wed Sep 2 09:08:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1.pxi.spice b/cells/mux2/sky130_fd_sc_hvl__mux2_1.pxi.spice
index 100fb91..7321e5a 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__mux2_1.pxi.spice
-* Created: Fri Aug 28 09:37:42 2020
+* Created: Wed Sep 2 09:08:10 2020
*
x_PM_SKY130_FD_SC_HVL__MUX2_1%VNB N_VNB_M1009_b VNB N_VNB_c_5_p VNB
+ PM_SKY130_FD_SC_HVL__MUX2_1%VNB
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1.spice b/cells/mux2/sky130_fd_sc_hvl__mux2_1.spice
index 40d2d19..dac6a1d 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1.spice
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__mux2_1.spice
-* Created: Fri Aug 28 09:37:42 2020
+* Created: Wed Sep 2 09:08:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1.lvs.report b/cells/mux4/sky130_fd_sc_hvl__mux4_1.lvs.report
new file mode 100644
index 0000000..454ed8e
--- /dev/null
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__mux4_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__mux4_1.sp ('sky130_fd_sc_hvl__mux4_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/mux4/sky130_fd_sc_hvl__mux4_1.spice ('sky130_fd_sc_hvl__mux4_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:08:14 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__mux4_1 sky130_fd_sc_hvl__mux4_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__mux4_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__mux4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 24 24
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 16 16
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 5 5 0 0 MN(NHV)
+ 5 5 0 0 MP(PHV)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S0 A2 A3 A1 A0 S1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1.pex.spice b/cells/mux4/sky130_fd_sc_hvl__mux4_1.pex.spice
index 51a4df2..8a75ca8 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1.pex.spice
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__mux4_1.pex.spice
-* Created: Fri Aug 28 09:37:49 2020
+* Created: Wed Sep 2 09:08:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1.pxi.spice b/cells/mux4/sky130_fd_sc_hvl__mux4_1.pxi.spice
index 61f8f9d..91de0ec 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1.pxi.spice
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__mux4_1.pxi.spice
-* Created: Fri Aug 28 09:37:49 2020
+* Created: Wed Sep 2 09:08:17 2020
*
x_PM_SKY130_FD_SC_HVL__MUX4_1%VNB N_VNB_M1020_b VNB N_VNB_c_3_p VNB
+ PM_SKY130_FD_SC_HVL__MUX4_1%VNB
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1.spice b/cells/mux4/sky130_fd_sc_hvl__mux4_1.spice
index 2e89cd2..a2825b8 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1.spice
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__mux4_1.spice
-* Created: Fri Aug 28 09:37:49 2020
+* Created: Wed Sep 2 09:08:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1.lvs.report b/cells/nand2/sky130_fd_sc_hvl__nand2_1.lvs.report
new file mode 100644
index 0000000..5279b8f
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__nand2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__nand2_1.sp ('sky130_fd_sc_hvl__nand2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/nand2/sky130_fd_sc_hvl__nand2_1.spice ('sky130_fd_sc_hvl__nand2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:08:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__nand2_1 sky130_fd_sc_hvl__nand2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__nand2_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__nand2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHV)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1.pex.spice b/cells/nand2/sky130_fd_sc_hvl__nand2_1.pex.spice
index f94ae7a..cd09ec8 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1.pex.spice
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__nand2_1.pex.spice
-* Created: Fri Aug 28 09:37:57 2020
+* Created: Wed Sep 2 09:08:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1.pxi.spice b/cells/nand2/sky130_fd_sc_hvl__nand2_1.pxi.spice
index df83c13..2baadc6 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__nand2_1.pxi.spice
-* Created: Fri Aug 28 09:37:57 2020
+* Created: Wed Sep 2 09:08:24 2020
*
x_PM_SKY130_FD_SC_HVL__NAND2_1%VNB N_VNB_M1000_b VNB N_VNB_c_4_p VNB
+ PM_SKY130_FD_SC_HVL__NAND2_1%VNB
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1.spice b/cells/nand2/sky130_fd_sc_hvl__nand2_1.spice
index 7e047db..88d57d3 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1.spice
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__nand2_1.spice
-* Created: Fri Aug 28 09:37:57 2020
+* Created: Wed Sep 2 09:08:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1.lvs.report b/cells/nand3/sky130_fd_sc_hvl__nand3_1.lvs.report
new file mode 100644
index 0000000..bb4c681
--- /dev/null
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__nand3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__nand3_1.sp ('sky130_fd_sc_hvl__nand3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/nand3/sky130_fd_sc_hvl__nand3_1.spice ('sky130_fd_sc_hvl__nand3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:08:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__nand3_1 sky130_fd_sc_hvl__nand3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__nand3_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__nand3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHV)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1.pex.spice b/cells/nand3/sky130_fd_sc_hvl__nand3_1.pex.spice
index 5ca3e47..d622c4b 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1.pex.spice
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__nand3_1.pex.spice
-* Created: Fri Aug 28 09:38:04 2020
+* Created: Wed Sep 2 09:08:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1.pxi.spice b/cells/nand3/sky130_fd_sc_hvl__nand3_1.pxi.spice
index 4696c5e..604339f 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1.pxi.spice
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__nand3_1.pxi.spice
-* Created: Fri Aug 28 09:38:04 2020
+* Created: Wed Sep 2 09:08:31 2020
*
x_PM_SKY130_FD_SC_HVL__NAND3_1%VNB N_VNB_M1002_b VNB N_VNB_c_7_p VNB
+ PM_SKY130_FD_SC_HVL__NAND3_1%VNB
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1.spice b/cells/nand3/sky130_fd_sc_hvl__nand3_1.spice
index c4289d2..8050659 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1.spice
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__nand3_1.spice
-* Created: Fri Aug 28 09:38:04 2020
+* Created: Wed Sep 2 09:08:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1.lvs.report b/cells/nor2/sky130_fd_sc_hvl__nor2_1.lvs.report
new file mode 100644
index 0000000..2961ec8
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__nor2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__nor2_1.sp ('sky130_fd_sc_hvl__nor2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/nor2/sky130_fd_sc_hvl__nor2_1.spice ('sky130_fd_sc_hvl__nor2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:08:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__nor2_1 sky130_fd_sc_hvl__nor2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__nor2_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__nor2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NHV)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1.pex.spice b/cells/nor2/sky130_fd_sc_hvl__nor2_1.pex.spice
index c2e6f81..45e09b7 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1.pex.spice
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__nor2_1.pex.spice
-* Created: Fri Aug 28 09:38:11 2020
+* Created: Wed Sep 2 09:08:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1.pxi.spice b/cells/nor2/sky130_fd_sc_hvl__nor2_1.pxi.spice
index 714e888..4c351b0 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__nor2_1.pxi.spice
-* Created: Fri Aug 28 09:38:11 2020
+* Created: Wed Sep 2 09:08:38 2020
*
x_PM_SKY130_FD_SC_HVL__NOR2_1%VNB N_VNB_M1002_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__NOR2_1%VNB
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1.spice b/cells/nor2/sky130_fd_sc_hvl__nor2_1.spice
index edf3108..85b57e6 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1.spice
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__nor2_1.spice
-* Created: Fri Aug 28 09:38:11 2020
+* Created: Wed Sep 2 09:08:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1.lvs.report b/cells/nor3/sky130_fd_sc_hvl__nor3_1.lvs.report
new file mode 100644
index 0000000..3be4d4a
--- /dev/null
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__nor3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__nor3_1.sp ('sky130_fd_sc_hvl__nor3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/nor3/sky130_fd_sc_hvl__nor3_1.spice ('sky130_fd_sc_hvl__nor3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:08:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__nor3_1 sky130_fd_sc_hvl__nor3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__nor3_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__nor3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NHV)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1.pex.spice b/cells/nor3/sky130_fd_sc_hvl__nor3_1.pex.spice
index b33e9f0..c43ca2c 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1.pex.spice
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__nor3_1.pex.spice
-* Created: Fri Aug 28 09:38:18 2020
+* Created: Wed Sep 2 09:08:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1.pxi.spice b/cells/nor3/sky130_fd_sc_hvl__nor3_1.pxi.spice
index 039b900..b5a8222 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1.pxi.spice
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__nor3_1.pxi.spice
-* Created: Fri Aug 28 09:38:18 2020
+* Created: Wed Sep 2 09:08:45 2020
*
x_PM_SKY130_FD_SC_HVL__NOR3_1%VNB N_VNB_M1003_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__NOR3_1%VNB
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1.spice b/cells/nor3/sky130_fd_sc_hvl__nor3_1.spice
index d0221c2..407554c 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1.spice
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__nor3_1.spice
-* Created: Fri Aug 28 09:38:18 2020
+* Created: Wed Sep 2 09:08:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1.lvs.report b/cells/o21a/sky130_fd_sc_hvl__o21a_1.lvs.report
new file mode 100644
index 0000000..d123265
--- /dev/null
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__o21a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__o21a_1.sp ('sky130_fd_sc_hvl__o21a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/o21a/sky130_fd_sc_hvl__o21a_1.spice ('sky130_fd_sc_hvl__o21a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:08:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__o21a_1 sky130_fd_sc_hvl__o21a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__o21a_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__o21a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 2 2 0 0 MP(PHV)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1.pex.spice b/cells/o21a/sky130_fd_sc_hvl__o21a_1.pex.spice
index a620641..e406daa 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1.pex.spice
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__o21a_1.pex.spice
-* Created: Fri Aug 28 09:38:34 2020
+* Created: Wed Sep 2 09:08:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1.pxi.spice b/cells/o21a/sky130_fd_sc_hvl__o21a_1.pxi.spice
index c80964a..1772358 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1.pxi.spice
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__o21a_1.pxi.spice
-* Created: Fri Aug 28 09:38:34 2020
+* Created: Wed Sep 2 09:08:52 2020
*
x_PM_SKY130_FD_SC_HVL__O21A_1%VNB N_VNB_M1000_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__O21A_1%VNB
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1.spice b/cells/o21a/sky130_fd_sc_hvl__o21a_1.spice
index c3fdd8a..2fc6993 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1.spice
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__o21a_1.spice
-* Created: Fri Aug 28 09:38:34 2020
+* Created: Wed Sep 2 09:08:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.lvs.report b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.lvs.report
new file mode 100644
index 0000000..0d7e0a0
--- /dev/null
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__o21ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__o21ai_1.sp ('sky130_fd_sc_hvl__o21ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.spice ('sky130_fd_sc_hvl__o21ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:08:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__o21ai_1 sky130_fd_sc_hvl__o21ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__o21ai_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__o21ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MP(PHV)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.pex.spice b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.pex.spice
index ba57891..2db8c9b 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.pex.spice
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__o21ai_1.pex.spice
-* Created: Fri Aug 28 09:38:41 2020
+* Created: Wed Sep 2 09:08:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.pxi.spice b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.pxi.spice
index 898060f..acc46c0 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.pxi.spice
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__o21ai_1.pxi.spice
-* Created: Fri Aug 28 09:38:41 2020
+* Created: Wed Sep 2 09:08:59 2020
*
x_PM_SKY130_FD_SC_HVL__O21AI_1%VNB N_VNB_M1003_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__O21AI_1%VNB
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.spice b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.spice
index faa7135..86b2207 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.spice
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__o21ai_1.spice
-* Created: Fri Aug 28 09:38:41 2020
+* Created: Wed Sep 2 09:08:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1.lvs.report b/cells/o22a/sky130_fd_sc_hvl__o22a_1.lvs.report
new file mode 100644
index 0000000..2d15f20
--- /dev/null
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__o22a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__o22a_1.sp ('sky130_fd_sc_hvl__o22a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/o22a/sky130_fd_sc_hvl__o22a_1.spice ('sky130_fd_sc_hvl__o22a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:09:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__o22a_1 sky130_fd_sc_hvl__o22a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__o22a_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__o22a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NHV)
+ 1 1 0 0 MP(PHV)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 B1 B2 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1.pex.spice b/cells/o22a/sky130_fd_sc_hvl__o22a_1.pex.spice
index 0d778cf..91b8e07 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1.pex.spice
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__o22a_1.pex.spice
-* Created: Fri Aug 28 09:38:48 2020
+* Created: Wed Sep 2 09:09:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1.pxi.spice b/cells/o22a/sky130_fd_sc_hvl__o22a_1.pxi.spice
index 4081842..33408a9 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1.pxi.spice
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__o22a_1.pxi.spice
-* Created: Fri Aug 28 09:38:48 2020
+* Created: Wed Sep 2 09:09:06 2020
*
x_PM_SKY130_FD_SC_HVL__O22A_1%VNB N_VNB_M1003_b VNB N_VNB_c_4_p VNB
+ PM_SKY130_FD_SC_HVL__O22A_1%VNB
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1.spice b/cells/o22a/sky130_fd_sc_hvl__o22a_1.spice
index bda2116..9c54fdd 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1.spice
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__o22a_1.spice
-* Created: Fri Aug 28 09:38:48 2020
+* Created: Wed Sep 2 09:09:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.lvs.report b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.lvs.report
new file mode 100644
index 0000000..b1a18c9
--- /dev/null
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__o22ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__o22ai_1.sp ('sky130_fd_sc_hvl__o22ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.spice ('sky130_fd_sc_hvl__o22ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:09:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__o22ai_1 sky130_fd_sc_hvl__o22ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__o22ai_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__o22ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.pex.spice b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.pex.spice
index 11a5cea..f88d675 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.pex.spice
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__o22ai_1.pex.spice
-* Created: Fri Aug 28 09:38:55 2020
+* Created: Wed Sep 2 09:09:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.pxi.spice b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.pxi.spice
index 1a488db..cf05b85 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.pxi.spice
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__o22ai_1.pxi.spice
-* Created: Fri Aug 28 09:38:55 2020
+* Created: Wed Sep 2 09:09:13 2020
*
x_PM_SKY130_FD_SC_HVL__O22AI_1%VNB N_VNB_M1006_b VNB N_VNB_c_7_p VNB
+ PM_SKY130_FD_SC_HVL__O22AI_1%VNB
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.spice b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.spice
index 4d33533..d1ec0b8 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.spice
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__o22ai_1.spice
-* Created: Fri Aug 28 09:38:55 2020
+* Created: Wed Sep 2 09:09:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1.lvs.report b/cells/or2/sky130_fd_sc_hvl__or2_1.lvs.report
new file mode 100644
index 0000000..12316f1
--- /dev/null
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__or2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__or2_1.sp ('sky130_fd_sc_hvl__or2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/or2/sky130_fd_sc_hvl__or2_1.spice ('sky130_fd_sc_hvl__or2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:09:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__or2_1 sky130_fd_sc_hvl__or2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__or2_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__or2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NHV)
+ 1 1 0 0 MP(PHV)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1.pex.spice b/cells/or2/sky130_fd_sc_hvl__or2_1.pex.spice
index f719716..1f6b575 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1.pex.spice
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__or2_1.pex.spice
-* Created: Fri Aug 28 09:39:02 2020
+* Created: Wed Sep 2 09:09:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1.pxi.spice b/cells/or2/sky130_fd_sc_hvl__or2_1.pxi.spice
index 831563e..8450d99 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1.pxi.spice
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__or2_1.pxi.spice
-* Created: Fri Aug 28 09:39:02 2020
+* Created: Wed Sep 2 09:09:20 2020
*
x_PM_SKY130_FD_SC_HVL__OR2_1%VNB N_VNB_M1005_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__OR2_1%VNB
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1.spice b/cells/or2/sky130_fd_sc_hvl__or2_1.spice
index 6f61859..a49abfa 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1.spice
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__or2_1.spice
-* Created: Fri Aug 28 09:39:02 2020
+* Created: Wed Sep 2 09:09:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1.lvs.report b/cells/or3/sky130_fd_sc_hvl__or3_1.lvs.report
new file mode 100644
index 0000000..369b471
--- /dev/null
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__or3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__or3_1.sp ('sky130_fd_sc_hvl__or3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/or3/sky130_fd_sc_hvl__or3_1.spice ('sky130_fd_sc_hvl__or3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:09:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__or3_1 sky130_fd_sc_hvl__or3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__or3_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__or3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NHV)
+ 1 1 0 0 MP(PHV)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1.pex.spice b/cells/or3/sky130_fd_sc_hvl__or3_1.pex.spice
index 1558b9c..4e98622 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1.pex.spice
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__or3_1.pex.spice
-* Created: Fri Aug 28 09:39:09 2020
+* Created: Wed Sep 2 09:09:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1.pxi.spice b/cells/or3/sky130_fd_sc_hvl__or3_1.pxi.spice
index 2a78b53..28bc2e7 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1.pxi.spice
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__or3_1.pxi.spice
-* Created: Fri Aug 28 09:39:09 2020
+* Created: Wed Sep 2 09:09:28 2020
*
x_PM_SKY130_FD_SC_HVL__OR3_1%VNB N_VNB_M1007_b VNB N_VNB_c_4_p VNB
+ PM_SKY130_FD_SC_HVL__OR3_1%VNB
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1.spice b/cells/or3/sky130_fd_sc_hvl__or3_1.spice
index 0b8ce0c..6b0baae 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1.spice
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__or3_1.spice
-* Created: Fri Aug 28 09:39:09 2020
+* Created: Wed Sep 2 09:09:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.lvs.report b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.lvs.report
new file mode 100644
index 0000000..efaea62
--- /dev/null
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.lvs.report
@@ -0,0 +1,549 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__probe_p_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__probe_p_8.sp ('sky130_fd_sc_hvl__probe_p_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.spice ('sky130_fd_sc_hvl__probe_p_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:09:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets.
+ Error: Different numbers of instances.
+ Error: Connectivity errors.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_hvl__probe_p_8 sky130_fd_sc_hvl__probe_p_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets (see below).
+ Error: Different numbers of instances (see below).
+ Error: Connectivity errors.
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__probe_p_8
+SOURCE CELL NAME: sky130_fd_sc_hvl__probe_p_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 7 *
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * R (2 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 24 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 7 *
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * R (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT NETS
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 Net X X
+ --- 2 Connections On This Net --- --- 3 Connections On This Net ---
+ -------------------------- --------------------------
+
+ R23(3.290,2.620):neg ** missing connection **
+
+ ** missing connection ** M1001:d
+ ** missing connection ** M1000:d
+
+
+--------------------------------------------------------------------------------------------------------------
+
+ 2 Net 6 ** missing net **
+
+
+**************************************************************************************************************
+ INCORRECT INSTANCES
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 3 R23(3.290,2.620) R(SHORT) ** missing instance **
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 1 0
+
+ Instances: 2 2 0 0 MN(NHV)
+ 2 2 0 0 MP(PHV)
+ 0 0 1 0 R(SHORT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 1 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 22 layout mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+ 22 source mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR VGND X
+
+
+**************************************************************************************************************
+ DETAILED INSTANCE CONNECTIONS
+
+ LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ (This section contains detailed information about connections of
+ matched instances that are involved in net discrepancies).
+
+--------------------------------------------------------------------------------------------------------------
+
+ M3(3.130,0.705) MN(NHV) M1001 MN(NHV)
+ g: 4 g: a_45_443#
+ s: VGND s: VGND
+ b: VNB b: VNB
+ d: 6 ** missing net **
+ ** X ** d: X
+
+--------------------------------------------------------------------------------------------------------------
+
+ M14(3.130,2.215) MP(PHV) M1000 MP(PHV)
+ g: 4 g: a_45_443#
+ s: VPWR s: VPWR
+ b: VPB b: VPB
+ d: 6 ** missing net **
+ ** X ** d: X
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.pex.spice b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.pex.spice
index 70d54b0..e1fe12a 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.pex.spice
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__probe_p_8.pex.spice
-* Created: Fri Aug 28 09:39:22 2020
+* Created: Wed Sep 2 09:09:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.pxi.spice b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.pxi.spice
index 32f15b1..9f03d2e 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.pxi.spice
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__probe_p_8.pxi.spice
-* Created: Fri Aug 28 09:39:22 2020
+* Created: Wed Sep 2 09:09:42 2020
*
x_PM_SKY130_FD_SC_HVL__PROBE_P_8%VNB N_VNB_M1003_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__PROBE_P_8%VNB
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.spice b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.spice
index 9a15741..708d9a8 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.spice
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__probe_p_8.spice
-* Created: Fri Aug 28 09:39:22 2020
+* Created: Wed Sep 2 09:09:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.lvs.report b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.lvs.report
new file mode 100644
index 0000000..e01e563
--- /dev/null
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.lvs.report
@@ -0,0 +1,549 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__probec_p_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__probec_p_8.sp ('sky130_fd_sc_hvl__probec_p_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.spice ('sky130_fd_sc_hvl__probec_p_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:09:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets.
+ Error: Different numbers of instances.
+ Error: Connectivity errors.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_hvl__probec_p_8 sky130_fd_sc_hvl__probec_p_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of nets (see below).
+ Error: Different numbers of instances (see below).
+ Error: Connectivity errors.
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__probec_p_8
+SOURCE CELL NAME: sky130_fd_sc_hvl__probec_p_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 7 *
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * R (2 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 24 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 7 *
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * R (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT NETS
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 Net X X
+ --- 2 Connections On This Net --- --- 3 Connections On This Net ---
+ -------------------------- --------------------------
+
+ R23(4.160,1.235):pos ** missing connection **
+
+ ** missing connection ** M1001:d
+ ** missing connection ** M1000:d
+
+
+--------------------------------------------------------------------------------------------------------------
+
+ 2 Net 6 ** missing net **
+
+
+**************************************************************************************************************
+ INCORRECT INSTANCES
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 3 R23(4.160,1.235) R(SHORT) ** missing instance **
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 1 0
+
+ Instances: 2 2 0 0 MN(NHV)
+ 2 2 0 0 MP(PHV)
+ 0 0 1 0 R(SHORT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 1 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 22 layout mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+ 22 source mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR VGND X
+
+
+**************************************************************************************************************
+ DETAILED INSTANCE CONNECTIONS
+
+ LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ (This section contains detailed information about connections of
+ matched instances that are involved in net discrepancies).
+
+--------------------------------------------------------------------------------------------------------------
+
+ M3(3.130,0.705) MN(NHV) M1001 MN(NHV)
+ g: 4 g: a_45_443#
+ s: VGND s: VGND
+ b: VNB b: VNB
+ d: 6 ** missing net **
+ ** X ** d: X
+
+--------------------------------------------------------------------------------------------------------------
+
+ M14(3.130,2.215) MP(PHV) M1000 MP(PHV)
+ g: 4 g: a_45_443#
+ s: VPWR s: VPWR
+ b: VPB b: VPB
+ d: 6 ** missing net **
+ ** X ** d: X
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.pex.spice b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.pex.spice
index ba7d0f8..b974435 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.pex.spice
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__probec_p_8.pex.spice
-* Created: Fri Aug 28 09:39:15 2020
+* Created: Wed Sep 2 09:09:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.pxi.spice b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.pxi.spice
index be37785..20e13e7 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.pxi.spice
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__probec_p_8.pxi.spice
-* Created: Fri Aug 28 09:39:15 2020
+* Created: Wed Sep 2 09:09:35 2020
*
x_PM_SKY130_FD_SC_HVL__PROBEC_P_8%VNB N_VNB_M1003_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__PROBEC_P_8%VNB
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.spice b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.spice
index e72b839..f6a88dc 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.spice
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__probec_p_8.spice
-* Created: Fri Aug 28 09:39:15 2020
+* Created: Wed Sep 2 09:09:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.lvs.report b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.lvs.report
new file mode 100644
index 0000000..d28d64b
--- /dev/null
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__schmittbuf_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__schmittbuf_1.sp ('sky130_fd_sc_hvl__schmittbuf_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.spice ('sky130_fd_sc_hvl__schmittbuf_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:09:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__schmittbuf_1 sky130_fd_sc_hvl__schmittbuf_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__schmittbuf_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__schmittbuf_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 2 2 R (2 pins)
+ 3 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 2 2 R (2 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NHV)
+ 4 4 0 0 MP(PHV)
+ 1 1 0 0 R(MRDN_HV)
+ 1 1 0 0 R(MRDP_HV)
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 3 layout instances were filtered and their pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.pex.spice b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.pex.spice
index 6367f7e..cba0450 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.pex.spice
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__schmittbuf_1.pex.spice
-* Created: Fri Aug 28 09:39:37 2020
+* Created: Wed Sep 2 09:09:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.pxi.spice b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.pxi.spice
index 7d5c6c9..4725849 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.pxi.spice
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__schmittbuf_1.pxi.spice
-* Created: Fri Aug 28 09:39:37 2020
+* Created: Wed Sep 2 09:09:49 2020
*
x_PM_SKY130_FD_SC_HVL__SCHMITTBUF_1%VNB N_VNB_M1001_b VNB N_VNB_c_4_p VNB
+ PM_SKY130_FD_SC_HVL__SCHMITTBUF_1%VNB
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.spice b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.spice
index e457c02..70fdf97 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.spice
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__schmittbuf_1.spice
-* Created: Fri Aug 28 09:39:37 2020
+* Created: Wed Sep 2 09:09:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.lvs.report b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.lvs.report
new file mode 100644
index 0000000..123b0b8
--- /dev/null
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.lvs.report
@@ -0,0 +1,472 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__sdfrbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__sdfrbp_1.sp ('sky130_fd_sc_hvl__sdfrbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.spice ('sky130_fd_sc_hvl__sdfrbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:09:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__sdfrbp_1 sky130_fd_sc_hvl__sdfrbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__sdfrbp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__sdfrbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 31 31
+
+ Instances: 21 21 MN (4 pins)
+ 21 21 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 43 42
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 20 20
+
+ Instances: 9 9 MN (4 pins)
+ 13 13 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 9 9 0 0 MN(NHV)
+ 13 13 0 0 MP(PHV)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.pex.spice b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.pex.spice
index 859fa67..5aa43b3 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.pex.spice
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfrbp_1.pex.spice
-* Created: Fri Aug 28 09:39:44 2020
+* Created: Wed Sep 2 09:09:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.pxi.spice b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.pxi.spice
index 9a9dd9d..ee6a7ad 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.pxi.spice
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfrbp_1.pxi.spice
-* Created: Fri Aug 28 09:39:44 2020
+* Created: Wed Sep 2 09:09:56 2020
*
x_PM_SKY130_FD_SC_HVL__SDFRBP_1%VNB N_VNB_M1029_b VNB N_VNB_c_3_p
+ PM_SKY130_FD_SC_HVL__SDFRBP_1%VNB
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.spice b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.spice
index 0bf9237..8400ba8 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.spice
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfrbp_1.spice
-* Created: Fri Aug 28 09:39:44 2020
+* Created: Wed Sep 2 09:09:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.lvs.report b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.lvs.report
new file mode 100644
index 0000000..40229ec
--- /dev/null
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.lvs.report
@@ -0,0 +1,472 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__sdfrtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__sdfrtp_1.sp ('sky130_fd_sc_hvl__sdfrtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.spice ('sky130_fd_sc_hvl__sdfrtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:10:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__sdfrtp_1 sky130_fd_sc_hvl__sdfrtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__sdfrtp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__sdfrtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 30 30
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NHV)
+ 12 12 0 0 MP(PHV)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCD SCE D RESET_B CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.pex.spice b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.pex.spice
index 13a6293..3a65212 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.pex.spice
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfrtp_1.pex.spice
-* Created: Fri Aug 28 09:39:52 2020
+* Created: Wed Sep 2 09:10:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.pxi.spice b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.pxi.spice
index 87bd0f6..b90c326 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.pxi.spice
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfrtp_1.pxi.spice
-* Created: Fri Aug 28 09:39:52 2020
+* Created: Wed Sep 2 09:10:03 2020
*
x_PM_SKY130_FD_SC_HVL__SDFRTP_1%VNB N_VNB_M1002_b VNB N_VNB_c_8_p
+ PM_SKY130_FD_SC_HVL__SDFRTP_1%VNB
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.spice b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.spice
index a6f7450..aabeac2 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.spice
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfrtp_1.spice
-* Created: Fri Aug 28 09:39:52 2020
+* Created: Wed Sep 2 09:10:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.lvs.report b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.lvs.report
new file mode 100644
index 0000000..c550b05
--- /dev/null
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__sdfsbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__sdfsbp_1.sp ('sky130_fd_sc_hvl__sdfsbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.spice ('sky130_fd_sc_hvl__sdfsbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:10:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__sdfsbp_1 sky130_fd_sc_hvl__sdfsbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__sdfsbp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__sdfsbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 32 32
+
+ Instances: 21 21 MN (4 pins)
+ 21 21 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 43 42
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 20 20
+
+ Instances: 8 8 MN (4 pins)
+ 11 11 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 8 8 0 0 MN(NHV)
+ 11 11 0 0 MP(PHV)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.pex.spice b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.pex.spice
index 074e930..4011d17 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.pex.spice
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfsbp_1.pex.spice
-* Created: Fri Aug 28 09:39:59 2020
+* Created: Wed Sep 2 09:10:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.pxi.spice b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.pxi.spice
index dfe9ab8..22cd4b4 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.pxi.spice
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfsbp_1.pxi.spice
-* Created: Fri Aug 28 09:39:59 2020
+* Created: Wed Sep 2 09:10:10 2020
*
x_PM_SKY130_FD_SC_HVL__SDFSBP_1%VNB N_VNB_M1014_b VNB N_VNB_c_2_p
+ PM_SKY130_FD_SC_HVL__SDFSBP_1%VNB
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.spice b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.spice
index 6f9c367..eab5c71 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.spice
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfsbp_1.spice
-* Created: Fri Aug 28 09:39:59 2020
+* Created: Wed Sep 2 09:10:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.lvs.report b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.lvs.report
new file mode 100644
index 0000000..f27ede0
--- /dev/null
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__sdfstp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__sdfstp_1.sp ('sky130_fd_sc_hvl__sdfstp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.spice ('sky130_fd_sc_hvl__sdfstp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:10:14 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__sdfstp_1 sky130_fd_sc_hvl__sdfstp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__sdfstp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__sdfstp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 31 31
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 7 7 0 0 MN(NHV)
+ 10 10 0 0 MP(PHV)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.pex.spice b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.pex.spice
index 851652c..36ca9c4 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.pex.spice
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfstp_1.pex.spice
-* Created: Fri Aug 28 09:40:06 2020
+* Created: Wed Sep 2 09:10:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.pxi.spice b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.pxi.spice
index 9882fa4..b680d34 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.pxi.spice
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfstp_1.pxi.spice
-* Created: Fri Aug 28 09:40:06 2020
+* Created: Wed Sep 2 09:10:18 2020
*
x_PM_SKY130_FD_SC_HVL__SDFSTP_1%VNB N_VNB_M1031_b VNB N_VNB_c_3_p
+ PM_SKY130_FD_SC_HVL__SDFSTP_1%VNB
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.spice b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.spice
index 1c6c9bf..550ce95 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.spice
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfstp_1.spice
-* Created: Fri Aug 28 09:40:06 2020
+* Created: Wed Sep 2 09:10:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.lvs.report b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.lvs.report
new file mode 100644
index 0000000..5b7ea66
--- /dev/null
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__sdfxbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__sdfxbp_1.sp ('sky130_fd_sc_hvl__sdfxbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.spice ('sky130_fd_sc_hvl__sdfxbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:10:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__sdfxbp_1 sky130_fd_sc_hvl__sdfxbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__sdfxbp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__sdfxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 27 27
+
+ Instances: 18 18 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 10 10 0 0 MN(NHV)
+ 10 10 0 0 MP(PHV)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE SCD D CLK VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.pex.spice b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.pex.spice
index e71c1e4..f0bb690 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.pex.spice
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfxbp_1.pex.spice
-* Created: Fri Aug 28 09:40:14 2020
+* Created: Wed Sep 2 09:10:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.pxi.spice b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.pxi.spice
index 3e8162e..ddd1a3b 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.pxi.spice
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfxbp_1.pxi.spice
-* Created: Fri Aug 28 09:40:14 2020
+* Created: Wed Sep 2 09:10:25 2020
*
x_PM_SKY130_FD_SC_HVL__SDFXBP_1%VNB N_VNB_M1028_b VNB N_VNB_c_2_p
+ PM_SKY130_FD_SC_HVL__SDFXBP_1%VNB
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.spice b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.spice
index dfae476..0e9e14e 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.spice
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfxbp_1.spice
-* Created: Fri Aug 28 09:40:14 2020
+* Created: Wed Sep 2 09:10:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.lvs.report b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.lvs.report
new file mode 100644
index 0000000..c0811d5
--- /dev/null
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__sdfxtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__sdfxtp_1.sp ('sky130_fd_sc_hvl__sdfxtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.spice ('sky130_fd_sc_hvl__sdfxtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:10:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__sdfxtp_1 sky130_fd_sc_hvl__sdfxtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__sdfxtp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__sdfxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 25 25
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NHV)
+ 8 8 0 0 MP(PHV)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.pex.spice b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.pex.spice
index 7306fba..86a5b93 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.pex.spice
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfxtp_1.pex.spice
-* Created: Fri Aug 28 09:40:21 2020
+* Created: Wed Sep 2 09:10:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.pxi.spice b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.pxi.spice
index c416896..552d3ec 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.pxi.spice
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfxtp_1.pxi.spice
-* Created: Fri Aug 28 09:40:21 2020
+* Created: Wed Sep 2 09:10:32 2020
*
x_PM_SKY130_FD_SC_HVL__SDFXTP_1%VNB N_VNB_M1011_b VNB N_VNB_c_2_p
+ PM_SKY130_FD_SC_HVL__SDFXTP_1%VNB
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.spice b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.spice
index c3185a9..21c3806 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.spice
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdfxtp_1.spice
-* Created: Fri Aug 28 09:40:21 2020
+* Created: Wed Sep 2 09:10:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.lvs.report b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.lvs.report
new file mode 100644
index 0000000..ce9de7d
--- /dev/null
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__sdlclkp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__sdlclkp_1.sp ('sky130_fd_sc_hvl__sdlclkp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.spice ('sky130_fd_sc_hvl__sdlclkp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:10:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__sdlclkp_1 sky130_fd_sc_hvl__sdlclkp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__sdlclkp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__sdlclkp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 7 7 0 0 MN(NHV)
+ 7 7 0 0 MP(PHV)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.pex.spice b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.pex.spice
index 623990a..80fc49a 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.pex.spice
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdlclkp_1.pex.spice
-* Created: Fri Aug 28 09:40:28 2020
+* Created: Wed Sep 2 09:10:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.pxi.spice b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.pxi.spice
index 8f7c4cb..1032d27 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.pxi.spice
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdlclkp_1.pxi.spice
-* Created: Fri Aug 28 09:40:28 2020
+* Created: Wed Sep 2 09:10:39 2020
*
x_PM_SKY130_FD_SC_HVL__SDLCLKP_1%VNB N_VNB_M1002_b VNB N_VNB_c_4_p VNB
+ PM_SKY130_FD_SC_HVL__SDLCLKP_1%VNB
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.spice b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.spice
index 6249e20..42204cc 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.spice
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdlclkp_1.spice
-* Created: Fri Aug 28 09:40:28 2020
+* Created: Wed Sep 2 09:10:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.lvs.report b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.lvs.report
new file mode 100644
index 0000000..9839c77
--- /dev/null
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__sdlxtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__sdlxtp_1.sp ('sky130_fd_sc_hvl__sdlxtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.spice ('sky130_fd_sc_hvl__sdlxtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:10:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__sdlxtp_1 sky130_fd_sc_hvl__sdlxtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__sdlxtp_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__sdlxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 21 21
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 6 6 0 0 MN(NHV)
+ 6 6 0 0 MP(PHV)
+ 3 3 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD GATE VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.pex.spice b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.pex.spice
index 3e5d1df..3862906 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.pex.spice
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdlxtp_1.pex.spice
-* Created: Fri Aug 28 09:40:44 2020
+* Created: Wed Sep 2 09:10:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.pxi.spice b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.pxi.spice
index 3273659..8d6ba4c 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.pxi.spice
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdlxtp_1.pxi.spice
-* Created: Fri Aug 28 09:40:44 2020
+* Created: Wed Sep 2 09:10:46 2020
*
x_PM_SKY130_FD_SC_HVL__SDLXTP_1%VNB N_VNB_M1004_b VNB N_VNB_c_2_p VNB
+ PM_SKY130_FD_SC_HVL__SDLXTP_1%VNB
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.spice b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.spice
index 85d255a..ebcb631 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.spice
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__sdlxtp_1.spice
-* Created: Fri Aug 28 09:40:44 2020
+* Created: Wed Sep 2 09:10:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.lvs.report b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.lvs.report
new file mode 100644
index 0000000..bcdea58
--- /dev/null
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__xnor2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__xnor2_1.sp ('sky130_fd_sc_hvl__xnor2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.spice ('sky130_fd_sc_hvl__xnor2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:10:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__xnor2_1 sky130_fd_sc_hvl__xnor2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__xnor2_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__xnor2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHV)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.pex.spice b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.pex.spice
index c193bc4..23986c9 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.pex.spice
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__xnor2_1.pex.spice
-* Created: Fri Aug 28 09:40:51 2020
+* Created: Wed Sep 2 09:10:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.pxi.spice b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.pxi.spice
index 44b5a1a..d14ba9f 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.pxi.spice
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__xnor2_1.pxi.spice
-* Created: Fri Aug 28 09:40:51 2020
+* Created: Wed Sep 2 09:10:53 2020
*
x_PM_SKY130_FD_SC_HVL__XNOR2_1%VNB N_VNB_M1004_b VNB N_VNB_c_4_p VNB
+ PM_SKY130_FD_SC_HVL__XNOR2_1%VNB
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.spice b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.spice
index bf0b0de..64fe49f 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.spice
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__xnor2_1.spice
-* Created: Fri Aug 28 09:40:51 2020
+* Created: Wed Sep 2 09:10:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1.lvs.report b/cells/xor2/sky130_fd_sc_hvl__xor2_1.lvs.report
new file mode 100644
index 0000000..500b844
--- /dev/null
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_hvl__xor2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_hvl__xor2_1.sp ('sky130_fd_sc_hvl__xor2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hvl/cells/xor2/sky130_fd_sc_hvl__xor2_1.spice ('sky130_fd_sc_hvl__xor2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:10:57 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_hvl__xor2_1 sky130_fd_sc_hvl__xor2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_hvl__xor2_1
+SOURCE CELL NAME: sky130_fd_sc_hvl__xor2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NHV)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1.pex.spice b/cells/xor2/sky130_fd_sc_hvl__xor2_1.pex.spice
index ff6cf69..55459aa 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1.pex.spice
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__xor2_1.pex.spice
-* Created: Fri Aug 28 09:40:58 2020
+* Created: Wed Sep 2 09:11:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1.pxi.spice b/cells/xor2/sky130_fd_sc_hvl__xor2_1.pxi.spice
index c9e6c88..9847000 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1.pxi.spice
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__xor2_1.pxi.spice
-* Created: Fri Aug 28 09:40:58 2020
+* Created: Wed Sep 2 09:11:00 2020
*
x_PM_SKY130_FD_SC_HVL__XOR2_1%VNB N_VNB_M1005_b VNB N_VNB_c_5_p VNB
+ PM_SKY130_FD_SC_HVL__XOR2_1%VNB
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1.spice b/cells/xor2/sky130_fd_sc_hvl__xor2_1.spice
index 3d5b181..663c597 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1.spice
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_hvl__xor2_1.spice
-* Created: Fri Aug 28 09:40:58 2020
+* Created: Wed Sep 2 09:11:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
