verilog: Fixing usage of cell reserved word.

`cell` is a Verilog reserved word.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
tree: 3a26ac8e255151161b9b8adc59bcc29eaa25dd67
  1. cells/
  2. models/
  3. tech/
  4. timing/
  5. .gitignore
  6. LICENSE
  7. README.rst