commit | c54a9afeeb0a1ed1805569e94e14d0eacd3e4580 | [log] [tgz] |
---|---|---|
author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
tree | e0c025ea02ef6a9ff7e7cce1133540557a1dd3ce | |
parent | f604d5b734086bac04177577e3f07b4962efc29e [diff] |
verilog: Fixing usage of cell reserved word. `cell` is a Verilog reserved word. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>