verilog: Fixing ordering of ports in primitives.
Verilog requires the first signal in a primitive's pin list must be the output.
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
diff --git a/models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.blackbox.v b/models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.blackbox.v
index e636077..3e8b262 100644
--- a/models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.blackbox.v
+++ b/models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.blackbox.v
@@ -32,22 +32,22 @@
(* blackbox *)
module sky130_fd_sc_hvl__udp_mux_4to2 (
+ X ,
A0,
A1,
A2,
A3,
S0,
- S1,
- X
+ S1
);
+ output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
- output X ;
endmodule
`default_nettype wire
diff --git a/models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.v b/models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.v
index 6579adc..764d1c1 100644
--- a/models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.v
+++ b/models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.v
@@ -34,22 +34,22 @@
`include "./sky130_fd_sc_hvl__udp_mux_4to2.blackbox.v"
`else
primitive sky130_fd_sc_hvl__udp_mux_4to2 (
+ X ,
A0,
A1,
A2,
A3,
S0,
- S1,
- X
+ S1
);
+ output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
- output X ;
table
// A0 A1 A2 A3 S0 S1 : X
