| commit | 1d151b8713474e01b9d74b266007b6598ef6db83 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | 6c256cf82f627e40d620192667310e1296081df0 | |
| parent | 6e32d91c543027c9f057b246f4bab41bbc470bcb [diff] | |
| parent | 632c15f0b75ef314b839980040240bb3982c0c80 [diff] |
verilog: Fixing usage of cell reserved word. `cell` is a Verilog reserved word. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>