commit | 632c15f0b75ef314b839980040240bb3982c0c80 | [log] [tgz] |
---|---|---|
author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
tree | 6898c5145692c31665ab0510e856dc9fede33079 | |
parent | 3c7f2248f1cc7db237a8cb98e6dbeece900e3793 [diff] |
verilog: Fixing usage of cell reserved word. `cell` is a Verilog reserved word. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>