tree 6c256cf82f627e40d620192667310e1296081df0
parent 6e32d91c543027c9f057b246f4bab41bbc470bcb
parent 632c15f0b75ef314b839980040240bb3982c0c80
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing usage of cell reserved word.

`cell` is a Verilog reserved word.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>