| commit | 7abde00cd31d510c8bf984c525f2908003978be7 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | 2453b546e60c8e5656e28072d82f23a716acede3 | |
| parent | 1dc32e3940b584a6ef4356aa7c4131920d991bf3 [diff] | |
| parent | 05d4cd52b636938bf1f2b6db61e995e3b71bb073 [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>