tree 2453b546e60c8e5656e28072d82f23a716acede3
parent 1dc32e3940b584a6ef4356aa7c4131920d991bf3
parent 05d4cd52b636938bf1f2b6db61e995e3b71bb073
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing ordering of ports in primitives.

Verilog requires the first signal in a primitive's pin list must be the output.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>