verilog: Fixing usage of cell reserved word.

`cell` is a Verilog reserved word.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
tree: e3d5d3b4a8718051e3352a2ff9333a7aae290d1d
  1. cells/
  2. models/
  3. tech/
  4. timing/
  5. .gitignore
  6. LICENSE
  7. README.rst