Adding definition.json files
diff --git a/cells/addf/definition.json b/cells/addf/definition.json new file mode 100644 index 0000000..050ff93 --- /dev/null +++ b/cells/addf/definition.json
@@ -0,0 +1,53 @@ +{ + "description": "Full Adder", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__addf", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "addf", + "parameters": [], + "ports": [ + [ + "signal", + "A", + "input", + "" + ], + [ + "signal", + "B", + "input", + "" + ], + [ + "signal", + "CI", + "input", + "" + ], + [ + "signal", + "CO", + "output", + "" + ], + [ + "signal", + "S", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__addf" +} \ No newline at end of file
diff --git a/cells/addh/definition.json b/cells/addh/definition.json new file mode 100644 index 0000000..062184b --- /dev/null +++ b/cells/addh/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "Half Adder", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__addh", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "addh", + "parameters": [], + "ports": [ + [ + "signal", + "A", + "input", + "" + ], + [ + "signal", + "B", + "input", + "" + ], + [ + "signal", + "CO", + "output", + "" + ], + [ + "signal", + "S", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__addh" +} \ No newline at end of file
diff --git a/cells/and2/definition.json b/cells/and2/definition.json new file mode 100644 index 0000000..1077ae4 --- /dev/null +++ b/cells/and2/definition.json
@@ -0,0 +1,41 @@ +{ + "description": "2-input AND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__and2", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "and2", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__and2" +} \ No newline at end of file
diff --git a/cells/and3/definition.json b/cells/and3/definition.json new file mode 100644 index 0000000..bcbdcf2 --- /dev/null +++ b/cells/and3/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "3-input AND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__and3", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "and3", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__and3" +} \ No newline at end of file
diff --git a/cells/and4/definition.json b/cells/and4/definition.json new file mode 100644 index 0000000..8a3a96a --- /dev/null +++ b/cells/and4/definition.json
@@ -0,0 +1,53 @@ +{ + "description": "4-input AND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__and4", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "and4", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "A4", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__and4" +} \ No newline at end of file
diff --git a/cells/antenna/definition.json b/cells/antenna/definition.json new file mode 100644 index 0000000..f8e8fa4 --- /dev/null +++ b/cells/antenna/definition.json
@@ -0,0 +1,29 @@ +{ + "description": "antenna cell", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__antenna", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "antenna", + "parameters": [], + "ports": [ + [ + "signal", + "I", + "input", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__antenna" +} \ No newline at end of file
diff --git a/cells/aoi21/definition.json b/cells/aoi21/definition.json new file mode 100644 index 0000000..a955143 --- /dev/null +++ b/cells/aoi21/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "2-input AND into 2-input NOR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__aoi21", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "aoi21", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "B", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__aoi21" +} \ No newline at end of file
diff --git a/cells/aoi211/definition.json b/cells/aoi211/definition.json new file mode 100644 index 0000000..9cb39f4 --- /dev/null +++ b/cells/aoi211/definition.json
@@ -0,0 +1,53 @@ +{ + "description": "2-input AND into 3-input NOR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__aoi211", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "aoi211", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "B", + "input", + "" + ], + [ + "signal", + "C", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__aoi211" +} \ No newline at end of file
diff --git a/cells/aoi22/definition.json b/cells/aoi22/definition.json new file mode 100644 index 0000000..6804d73 --- /dev/null +++ b/cells/aoi22/definition.json
@@ -0,0 +1,53 @@ +{ + "description": "two 2-input AND into 2-input NOR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__aoi22", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "aoi22", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "B1", + "input", + "" + ], + [ + "signal", + "B2", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__aoi22" +} \ No newline at end of file
diff --git a/cells/aoi221/definition.json b/cells/aoi221/definition.json new file mode 100644 index 0000000..920aa2d --- /dev/null +++ b/cells/aoi221/definition.json
@@ -0,0 +1,59 @@ +{ + "description": "two 2-input AND into 3-input NOR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__aoi221", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "aoi221", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "B1", + "input", + "" + ], + [ + "signal", + "B2", + "input", + "" + ], + [ + "signal", + "C", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__aoi221" +} \ No newline at end of file
diff --git a/cells/aoi222/definition.json b/cells/aoi222/definition.json new file mode 100644 index 0000000..0840655 --- /dev/null +++ b/cells/aoi222/definition.json
@@ -0,0 +1,65 @@ +{ + "description": "three 2-input AND into 3-input NOR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__aoi222", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "aoi222", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "B1", + "input", + "" + ], + [ + "signal", + "B2", + "input", + "" + ], + [ + "signal", + "C1", + "input", + "" + ], + [ + "signal", + "C2", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__aoi222" +} \ No newline at end of file
diff --git a/cells/buf/definition.json b/cells/buf/definition.json new file mode 100644 index 0000000..56b808a --- /dev/null +++ b/cells/buf/definition.json
@@ -0,0 +1,35 @@ +{ + "description": "buffer", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__buf", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "buf", + "parameters": [], + "ports": [ + [ + "signal", + "I", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__buf" +} \ No newline at end of file
diff --git a/cells/bufz/definition.json b/cells/bufz/definition.json new file mode 100644 index 0000000..e8547d9 --- /dev/null +++ b/cells/bufz/definition.json
@@ -0,0 +1,41 @@ +{ + "description": "tri-state buffer", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__bufz", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "bufz", + "parameters": [], + "ports": [ + [ + "signal", + "EN", + "input", + "" + ], + [ + "signal", + "I", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__bufz" +} \ No newline at end of file
diff --git a/cells/clkbuf/definition.json b/cells/clkbuf/definition.json new file mode 100644 index 0000000..f8497d4 --- /dev/null +++ b/cells/clkbuf/definition.json
@@ -0,0 +1,35 @@ +{ + "description": "clock buffer", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__clkbuf", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "clkbuf", + "parameters": [], + "ports": [ + [ + "signal", + "I", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__clkbuf" +} \ No newline at end of file
diff --git a/cells/clkinv/definition.json b/cells/clkinv/definition.json new file mode 100644 index 0000000..e026702 --- /dev/null +++ b/cells/clkinv/definition.json
@@ -0,0 +1,35 @@ +{ + "description": "clock inverter", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__clkinv", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "clkinv", + "parameters": [], + "ports": [ + [ + "signal", + "I", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__clkinv" +} \ No newline at end of file
diff --git a/cells/dffnq/definition.json b/cells/dffnq/definition.json new file mode 100644 index 0000000..f643022 --- /dev/null +++ b/cells/dffnq/definition.json
@@ -0,0 +1,41 @@ +{ + "description": "negative edge triggered D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "dffnq", + "parameters": [], + "ports": [ + [ + "signal", + "CLKN", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffnq" +} \ No newline at end of file
diff --git a/cells/dffnrnq/definition.json b/cells/dffnrnq/definition.json new file mode 100644 index 0000000..269eb7b --- /dev/null +++ b/cells/dffnrnq/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "negative edge triggered D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffnrnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "dffnrnq", + "parameters": [], + "ports": [ + [ + "signal", + "CLKN", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "RN", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffnrnq" +} \ No newline at end of file
diff --git a/cells/dffnrsnq/definition.json b/cells/dffnrsnq/definition.json new file mode 100644 index 0000000..328307f --- /dev/null +++ b/cells/dffnrsnq/definition.json
@@ -0,0 +1,53 @@ +{ + "description": "negative edge triggered D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffnrsnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "dffnrsnq", + "parameters": [], + "ports": [ + [ + "signal", + "CLKN", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "RN", + "input", + "" + ], + [ + "signal", + "SETN", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffnrsnq" +} \ No newline at end of file
diff --git a/cells/dffnsnq/definition.json b/cells/dffnsnq/definition.json new file mode 100644 index 0000000..f60624c --- /dev/null +++ b/cells/dffnsnq/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "negative edge triggered D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffnsnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "dffnsnq", + "parameters": [], + "ports": [ + [ + "signal", + "CLKN", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "SETN", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffnsnq" +} \ No newline at end of file
diff --git a/cells/dffq/definition.json b/cells/dffq/definition.json new file mode 100644 index 0000000..465a536 --- /dev/null +++ b/cells/dffq/definition.json
@@ -0,0 +1,41 @@ +{ + "description": "poistive edge triggered D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "dffq", + "parameters": [], + "ports": [ + [ + "signal", + "CLK", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffq" +} \ No newline at end of file
diff --git a/cells/dffrnq/definition.json b/cells/dffrnq/definition.json new file mode 100644 index 0000000..1e3fa6c --- /dev/null +++ b/cells/dffrnq/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "positive edge triggered D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffrnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "dffrnq", + "parameters": [], + "ports": [ + [ + "signal", + "CLK", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "RN", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffrnq" +} \ No newline at end of file
diff --git a/cells/dffrsnq/definition.json b/cells/dffrsnq/definition.json new file mode 100644 index 0000000..0768fad --- /dev/null +++ b/cells/dffrsnq/definition.json
@@ -0,0 +1,53 @@ +{ + "description": "positive edge triggered D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffrsnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "dffrsnq", + "parameters": [], + "ports": [ + [ + "signal", + "CLK", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "RN", + "input", + "" + ], + [ + "signal", + "SETN", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffrsnq" +} \ No newline at end of file
diff --git a/cells/dffsnq/definition.json b/cells/dffsnq/definition.json new file mode 100644 index 0000000..ec33723 --- /dev/null +++ b/cells/dffsnq/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "positive edge triggered D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dffsnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "dffsnq", + "parameters": [], + "ports": [ + [ + "signal", + "CLK", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "SETN", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dffsnq" +} \ No newline at end of file
diff --git a/cells/dlya/definition.json b/cells/dlya/definition.json new file mode 100644 index 0000000..35f3b09 --- /dev/null +++ b/cells/dlya/definition.json
@@ -0,0 +1,35 @@ +{ + "description": "2 buffer delay cell", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dlya", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "dlya", + "parameters": [], + "ports": [ + [ + "signal", + "I", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dlya" +} \ No newline at end of file
diff --git a/cells/dlyb/definition.json b/cells/dlyb/definition.json new file mode 100644 index 0000000..25e76e3 --- /dev/null +++ b/cells/dlyb/definition.json
@@ -0,0 +1,35 @@ +{ + "description": "4 buffer delay cell", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dlyb", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "dlyb", + "parameters": [], + "ports": [ + [ + "signal", + "I", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dlyb" +} \ No newline at end of file
diff --git a/cells/dlyc/definition.json b/cells/dlyc/definition.json new file mode 100644 index 0000000..516977e --- /dev/null +++ b/cells/dlyc/definition.json
@@ -0,0 +1,35 @@ +{ + "description": "8 buffer delay cell", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dlyc", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "dlyc", + "parameters": [], + "ports": [ + [ + "signal", + "I", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dlyc" +} \ No newline at end of file
diff --git a/cells/dlyd/definition.json b/cells/dlyd/definition.json new file mode 100644 index 0000000..b4f11b8 --- /dev/null +++ b/cells/dlyd/definition.json
@@ -0,0 +1,35 @@ +{ + "description": "16 buffer delay cell", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dlyd", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "dlyd", + "parameters": [], + "ports": [ + [ + "signal", + "I", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dlyd" +} \ No newline at end of file
diff --git a/cells/endcap/definition.json b/cells/endcap/definition.json new file mode 100644 index 0000000..061d34a --- /dev/null +++ b/cells/endcap/definition.json
@@ -0,0 +1,23 @@ +{ + "description": "row end closure cell", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__endcap", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "endcap", + "parameters": [], + "ports": [ + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__endcap" +} \ No newline at end of file
diff --git a/cells/fill/definition.json b/cells/fill/definition.json new file mode 100644 index 0000000..3677f8e --- /dev/null +++ b/cells/fill/definition.json
@@ -0,0 +1,23 @@ +{ + "description": "filler whose cell width is 0.56um", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__fill", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "fill", + "parameters": [], + "ports": [ + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__fill" +} \ No newline at end of file
diff --git a/cells/fillcap/definition.json b/cells/fillcap/definition.json new file mode 100644 index 0000000..a7e3a2e --- /dev/null +++ b/cells/fillcap/definition.json
@@ -0,0 +1,23 @@ +{ + "description": "filler whose cell width is 35.84um", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__fillcap", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "fillcap", + "parameters": [], + "ports": [ + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__fillcap" +} \ No newline at end of file
diff --git a/cells/filltie/definition.json b/cells/filltie/definition.json new file mode 100644 index 0000000..e003680 --- /dev/null +++ b/cells/filltie/definition.json
@@ -0,0 +1,23 @@ +{ + "description": "filler", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__filltie", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "filltie", + "parameters": [], + "ports": [ + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__filltie" +} \ No newline at end of file
diff --git a/cells/hold/definition.json b/cells/hold/definition.json new file mode 100644 index 0000000..06fc1b7 --- /dev/null +++ b/cells/hold/definition.json
@@ -0,0 +1,23 @@ +{ + "description": "state holder cell", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__hold", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "hold", + "parameters": [], + "ports": [ + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__hold" +} \ No newline at end of file
diff --git a/cells/icgtn/definition.json b/cells/icgtn/definition.json new file mode 100644 index 0000000..1e7fe70 --- /dev/null +++ b/cells/icgtn/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "negative-edge triggered clock-gating latch", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__icgtn", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "icgtn", + "parameters": [], + "ports": [ + [ + "signal", + "CLKN", + "input", + "" + ], + [ + "signal", + "E", + "input", + "" + ], + [ + "signal", + "TE", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__icgtn" +} \ No newline at end of file
diff --git a/cells/icgtp/definition.json b/cells/icgtp/definition.json new file mode 100644 index 0000000..2eea2ef --- /dev/null +++ b/cells/icgtp/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "positive-edge triggered clock-gating latch", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__icgtp", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "icgtp", + "parameters": [], + "ports": [ + [ + "signal", + "CLK", + "input", + "" + ], + [ + "signal", + "E", + "input", + "" + ], + [ + "signal", + "TE", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__icgtp" +} \ No newline at end of file
diff --git a/cells/inv/definition.json b/cells/inv/definition.json new file mode 100644 index 0000000..03b6e66 --- /dev/null +++ b/cells/inv/definition.json
@@ -0,0 +1,35 @@ +{ + "description": "inverter", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__inv", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "inv", + "parameters": [], + "ports": [ + [ + "signal", + "I", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__inv" +} \ No newline at end of file
diff --git a/cells/invz/definition.json b/cells/invz/definition.json new file mode 100644 index 0000000..3a54018 --- /dev/null +++ b/cells/invz/definition.json
@@ -0,0 +1,41 @@ +{ + "description": "tri-state inverter", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__invz", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "invz", + "parameters": [], + "ports": [ + [ + "signal", + "EN", + "input", + "" + ], + [ + "signal", + "I", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__invz" +} \ No newline at end of file
diff --git a/cells/latq/definition.json b/cells/latq/definition.json new file mode 100644 index 0000000..36a5a6e --- /dev/null +++ b/cells/latq/definition.json
@@ -0,0 +1,41 @@ +{ + "description": "positive D-latch", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__latq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "latq", + "parameters": [], + "ports": [ + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "E", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__latq" +} \ No newline at end of file
diff --git a/cells/latrnq/definition.json b/cells/latrnq/definition.json new file mode 100644 index 0000000..d2658f8 --- /dev/null +++ b/cells/latrnq/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "positive D-latch", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__latrnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "latrnq", + "parameters": [], + "ports": [ + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "E", + "input", + "" + ], + [ + "signal", + "RN", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__latrnq" +} \ No newline at end of file
diff --git a/cells/latrsnq/definition.json b/cells/latrsnq/definition.json new file mode 100644 index 0000000..5cf7c07 --- /dev/null +++ b/cells/latrsnq/definition.json
@@ -0,0 +1,53 @@ +{ + "description": "positive D-latch", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__latrsnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "latrsnq", + "parameters": [], + "ports": [ + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "E", + "input", + "" + ], + [ + "signal", + "RN", + "input", + "" + ], + [ + "signal", + "SETN", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__latrsnq" +} \ No newline at end of file
diff --git a/cells/latsnq/definition.json b/cells/latsnq/definition.json new file mode 100644 index 0000000..995f32a --- /dev/null +++ b/cells/latsnq/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "positive D-latch", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__latsnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "latsnq", + "parameters": [], + "ports": [ + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "E", + "input", + "" + ], + [ + "signal", + "SETN", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__latsnq" +} \ No newline at end of file
diff --git a/cells/mux2/definition.json b/cells/mux2/definition.json new file mode 100644 index 0000000..2a010e2 --- /dev/null +++ b/cells/mux2/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "2-to-1 multiplexer", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__mux2", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "mux2", + "parameters": [], + "ports": [ + [ + "signal", + "I0", + "input", + "" + ], + [ + "signal", + "I1", + "input", + "" + ], + [ + "signal", + "S", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__mux2" +} \ No newline at end of file
diff --git a/cells/mux4/definition.json b/cells/mux4/definition.json new file mode 100644 index 0000000..fb8678d --- /dev/null +++ b/cells/mux4/definition.json
@@ -0,0 +1,65 @@ +{ + "description": "4-to-1 multiplexer", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__mux4", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "mux4", + "parameters": [], + "ports": [ + [ + "signal", + "I0", + "input", + "" + ], + [ + "signal", + "I1", + "input", + "" + ], + [ + "signal", + "I2", + "input", + "" + ], + [ + "signal", + "I3", + "input", + "" + ], + [ + "signal", + "S0", + "input", + "" + ], + [ + "signal", + "S1", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__mux4" +} \ No newline at end of file
diff --git a/cells/nand2/definition.json b/cells/nand2/definition.json new file mode 100644 index 0000000..69c044a --- /dev/null +++ b/cells/nand2/definition.json
@@ -0,0 +1,41 @@ +{ + "description": "2-input NAND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__nand2", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "nand2", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__nand2" +} \ No newline at end of file
diff --git a/cells/nand3/definition.json b/cells/nand3/definition.json new file mode 100644 index 0000000..66659e8 --- /dev/null +++ b/cells/nand3/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "3-input NAND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__nand3", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "nand3", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__nand3" +} \ No newline at end of file
diff --git a/cells/nand4/definition.json b/cells/nand4/definition.json new file mode 100644 index 0000000..1342d84 --- /dev/null +++ b/cells/nand4/definition.json
@@ -0,0 +1,53 @@ +{ + "description": "4-input NAND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__nand4", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "nand4", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "A4", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__nand4" +} \ No newline at end of file
diff --git a/cells/nor2/definition.json b/cells/nor2/definition.json new file mode 100644 index 0000000..9c389f3 --- /dev/null +++ b/cells/nor2/definition.json
@@ -0,0 +1,41 @@ +{ + "description": "2-input NOR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__nor2", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "nor2", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__nor2" +} \ No newline at end of file
diff --git a/cells/nor3/definition.json b/cells/nor3/definition.json new file mode 100644 index 0000000..986c6e5 --- /dev/null +++ b/cells/nor3/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "3-input NOR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__nor3", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "nor3", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__nor3" +} \ No newline at end of file
diff --git a/cells/nor4/definition.json b/cells/nor4/definition.json new file mode 100644 index 0000000..51902e0 --- /dev/null +++ b/cells/nor4/definition.json
@@ -0,0 +1,53 @@ +{ + "description": "4-input NOR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__nor4", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "nor4", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "A4", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__nor4" +} \ No newline at end of file
diff --git a/cells/oai21/definition.json b/cells/oai21/definition.json new file mode 100644 index 0000000..cd14fcc --- /dev/null +++ b/cells/oai21/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "2-input OR into 2-input NAND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai21", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "oai21", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "B", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai21" +} \ No newline at end of file
diff --git a/cells/oai211/definition.json b/cells/oai211/definition.json new file mode 100644 index 0000000..6a280cf --- /dev/null +++ b/cells/oai211/definition.json
@@ -0,0 +1,53 @@ +{ + "description": "2-input OR into 3-input NAND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai211", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "oai211", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "B", + "input", + "" + ], + [ + "signal", + "C", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai211" +} \ No newline at end of file
diff --git a/cells/oai22/definition.json b/cells/oai22/definition.json new file mode 100644 index 0000000..65ad00b --- /dev/null +++ b/cells/oai22/definition.json
@@ -0,0 +1,53 @@ +{ + "description": "two 2-input OR into 2-input NAND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai22", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "oai22", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "B1", + "input", + "" + ], + [ + "signal", + "B2", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai22" +} \ No newline at end of file
diff --git a/cells/oai221/definition.json b/cells/oai221/definition.json new file mode 100644 index 0000000..338ce4e --- /dev/null +++ b/cells/oai221/definition.json
@@ -0,0 +1,59 @@ +{ + "description": "two 2-input OR into 3-input NAND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai221", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "oai221", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "B1", + "input", + "" + ], + [ + "signal", + "B2", + "input", + "" + ], + [ + "signal", + "C", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai221" +} \ No newline at end of file
diff --git a/cells/oai222/definition.json b/cells/oai222/definition.json new file mode 100644 index 0000000..72f539e --- /dev/null +++ b/cells/oai222/definition.json
@@ -0,0 +1,65 @@ +{ + "description": "three 2-input OR into 3-input NAND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai222", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "oai222", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "B1", + "input", + "" + ], + [ + "signal", + "B2", + "input", + "" + ], + [ + "signal", + "C1", + "input", + "" + ], + [ + "signal", + "C2", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai222" +} \ No newline at end of file
diff --git a/cells/oai31/definition.json b/cells/oai31/definition.json new file mode 100644 index 0000000..3d889f9 --- /dev/null +++ b/cells/oai31/definition.json
@@ -0,0 +1,53 @@ +{ + "description": "3-input OR into 2-input NAND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai31", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "oai31", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "B", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai31" +} \ No newline at end of file
diff --git a/cells/oai32/definition.json b/cells/oai32/definition.json new file mode 100644 index 0000000..5e57252 --- /dev/null +++ b/cells/oai32/definition.json
@@ -0,0 +1,59 @@ +{ + "description": "3-input OR and a 2-input OR into 2-input NAND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai32", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "oai32", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "B1", + "input", + "" + ], + [ + "signal", + "B2", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai32" +} \ No newline at end of file
diff --git a/cells/oai33/definition.json b/cells/oai33/definition.json new file mode 100644 index 0000000..ecfd623 --- /dev/null +++ b/cells/oai33/definition.json
@@ -0,0 +1,65 @@ +{ + "description": "two 3-input OR into 2-input NAND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__oai33", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "oai33", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "B1", + "input", + "" + ], + [ + "signal", + "B2", + "input", + "" + ], + [ + "signal", + "B3", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__oai33" +} \ No newline at end of file
diff --git a/cells/or2/definition.json b/cells/or2/definition.json new file mode 100644 index 0000000..4bd4a21 --- /dev/null +++ b/cells/or2/definition.json
@@ -0,0 +1,41 @@ +{ + "description": "2-input OR(A1", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__or2", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "or2", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__or2" +} \ No newline at end of file
diff --git a/cells/or3/definition.json b/cells/or3/definition.json new file mode 100644 index 0000000..6da33e1 --- /dev/null +++ b/cells/or3/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "3-input OR(A1", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__or3", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "or3", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__or3" +} \ No newline at end of file
diff --git a/cells/or4/definition.json b/cells/or4/definition.json new file mode 100644 index 0000000..1e19396 --- /dev/null +++ b/cells/or4/definition.json
@@ -0,0 +1,53 @@ +{ + "description": "4-input OR(A1", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__or4", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "or4", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "A4", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__or4" +} \ No newline at end of file
diff --git a/cells/sdffq/definition.json b/cells/sdffq/definition.json new file mode 100644 index 0000000..91cb17e --- /dev/null +++ b/cells/sdffq/definition.json
@@ -0,0 +1,53 @@ +{ + "description": "positive edge triggered scan D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__sdffq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "sdffq", + "parameters": [], + "ports": [ + [ + "signal", + "CLK", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "SE", + "input", + "" + ], + [ + "signal", + "SI", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__sdffq" +} \ No newline at end of file
diff --git a/cells/sdffrnq/definition.json b/cells/sdffrnq/definition.json new file mode 100644 index 0000000..c7f8869 --- /dev/null +++ b/cells/sdffrnq/definition.json
@@ -0,0 +1,59 @@ +{ + "description": "positive edge triggered scan D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__sdffrnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "sdffrnq", + "parameters": [], + "ports": [ + [ + "signal", + "CLK", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "RN", + "input", + "" + ], + [ + "signal", + "SE", + "input", + "" + ], + [ + "signal", + "SI", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__sdffrnq" +} \ No newline at end of file
diff --git a/cells/sdffrsnq/definition.json b/cells/sdffrsnq/definition.json new file mode 100644 index 0000000..96280ce --- /dev/null +++ b/cells/sdffrsnq/definition.json
@@ -0,0 +1,65 @@ +{ + "description": "positive edge triggered scan D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__sdffrsnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "sdffrsnq", + "parameters": [], + "ports": [ + [ + "signal", + "CLK", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "RN", + "input", + "" + ], + [ + "signal", + "SE", + "input", + "" + ], + [ + "signal", + "SETN", + "input", + "" + ], + [ + "signal", + "SI", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__sdffrsnq" +} \ No newline at end of file
diff --git a/cells/sdffsnq/definition.json b/cells/sdffsnq/definition.json new file mode 100644 index 0000000..0a1385e --- /dev/null +++ b/cells/sdffsnq/definition.json
@@ -0,0 +1,59 @@ +{ + "description": "positive edge triggered scan D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__sdffsnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "sdffsnq", + "parameters": [], + "ports": [ + [ + "signal", + "CLK", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "SE", + "input", + "" + ], + [ + "signal", + "SETN", + "input", + "" + ], + [ + "signal", + "SI", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__sdffsnq" +} \ No newline at end of file
diff --git a/cells/tieh/definition.json b/cells/tieh/definition.json new file mode 100644 index 0000000..447c77d --- /dev/null +++ b/cells/tieh/definition.json
@@ -0,0 +1,29 @@ +{ + "description": "high level generator", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__tieh", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "tieh", + "parameters": [], + "ports": [ + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__tieh" +} \ No newline at end of file
diff --git a/cells/tiel/definition.json b/cells/tiel/definition.json new file mode 100644 index 0000000..0c7d89e --- /dev/null +++ b/cells/tiel/definition.json
@@ -0,0 +1,29 @@ +{ + "description": "low level generator", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__tiel", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "tiel", + "parameters": [], + "ports": [ + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__tiel" +} \ No newline at end of file
diff --git a/cells/xnor2/definition.json b/cells/xnor2/definition.json new file mode 100644 index 0000000..49c49bf --- /dev/null +++ b/cells/xnor2/definition.json
@@ -0,0 +1,41 @@ +{ + "description": "2-input exclusive NOR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__xnor2", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "xnor2", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__xnor2" +} \ No newline at end of file
diff --git a/cells/xnor3/definition.json b/cells/xnor3/definition.json new file mode 100644 index 0000000..6bc11ae --- /dev/null +++ b/cells/xnor3/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "3-input exclusive NOR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__xnor3", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "xnor3", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__xnor3" +} \ No newline at end of file
diff --git a/cells/xor2/definition.json b/cells/xor2/definition.json new file mode 100644 index 0000000..844e26a --- /dev/null +++ b/cells/xor2/definition.json
@@ -0,0 +1,41 @@ +{ + "description": "2-input exclusive OR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__xor2", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "xor2", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__xor2" +} \ No newline at end of file
diff --git a/cells/xor3/definition.json b/cells/xor3/definition.json new file mode 100644 index 0000000..b79691b --- /dev/null +++ b/cells/xor3/definition.json
@@ -0,0 +1,47 @@ +{ + "description": "3-input exclusive OR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__xor3", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "xor3", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__xor3" +} \ No newline at end of file