blob: 1077ae4d81d6133586297e42f914d04eaefc627c [file] [log] [blame]
{
"description": "2-input AND",
"file_prefix": "gf180mcu_fd_sc_mcu7t5v0__and2",
"library": "gf180mcu_fd_sc_mcu7t5v0",
"name": "and2",
"parameters": [],
"ports": [
[
"signal",
"A1",
"input",
""
],
[
"signal",
"A2",
"input",
""
],
[
"signal",
"Z",
"output",
""
],
[
"power",
"VDD",
"input",
"supply1"
],
[
"power",
"VSS",
"input",
"supply0"
]
],
"type": "cell",
"verilog_name": "gf180mcu_fd_sc_mcu7t5v0__and2"
}