cells/dlyd/definition.json

{
    "description": "16 buffer delay cell",
    "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dlyd",
    "library": "gf180mcu_fd_sc_mcu7t5v0",
    "name": "dlyd",
    "parameters": [],
    "ports": [
        [
            "signal",
            "I",
            "input",
            ""
        ],
        [
            "signal",
            "Z",
            "output",
            ""
        ],
        [
            "power",
            "VDD",
            "input",
            "supply1"
        ],
        [
            "power",
            "VSS",
            "input",
            "supply0"
        ]
    ],
    "type": "cell",
    "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dlyd"
}