Fixing the functional schematic image reference.
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
diff --git a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x2.rst b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x2.rst
index 71e43d2..13f8fae 100644
--- a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x2.rst
+++ b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x2.rst
@@ -77,7 +77,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image11|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__addf_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x4.rst b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x4.rst
index 2731df1..288952e 100644
--- a/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x4.rst
+++ b/cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_x4.rst
@@ -77,7 +77,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image14|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__addf_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x1.rst b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x1.rst
index b363bae..74bf957 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x1.rst
+++ b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x1.rst
@@ -70,7 +70,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image17|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__addh_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x2.rst b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x2.rst
index 67eb02f..4ecc5aa 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x2.rst
+++ b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x2.rst
@@ -70,7 +70,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image20|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__addh_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x4.rst b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x4.rst
index 3d9a0e1..e815375 100644
--- a/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x4.rst
+++ b/cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_x4.rst
@@ -70,7 +70,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image23|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__addh_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x1.rst b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x1.rst
index f62f0a1..b93f51b 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x1.rst
+++ b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x1.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image26|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and2_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x2.rst b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x2.rst
index f435e8b..813494f 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x2.rst
+++ b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x2.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image29|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and2_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x4.rst b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x4.rst
index ca5ca1e..b43df40 100644
--- a/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x4.rst
+++ b/cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_x4.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image32|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and2_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x1.rst b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x1.rst
index 4542963..db34baa 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x1.rst
+++ b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x1.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image35|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and3_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x2.rst b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x2.rst
index 2408917..d06865b 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x2.rst
+++ b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x2.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image38|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and3_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x4.rst b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x4.rst
index 7398cd9..efdfba5 100644
--- a/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x4.rst
+++ b/cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_x4.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image41|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and3_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x1.rst b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x1.rst
index 9ef90f5..bf4da41 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x1.rst
+++ b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x1.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image44|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and4_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x2.rst b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x2.rst
index 3e8cfc5..e7e7a90 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x2.rst
+++ b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x2.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image47|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and4_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x4.rst b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x4.rst
index 07e2136..62b791c 100644
--- a/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x4.rst
+++ b/cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_x4.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image50|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__and4_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.rst b/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.rst
index cca6c4b..20c8b0e 100644
--- a/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.rst
+++ b/cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image53|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__antenna.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x1.rst b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x1.rst
index 4c6363a..8a92674 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x1.rst
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x1.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image65|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi21_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x2.rst b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x2.rst
index 9fc88a4..3fd41c3 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x2.rst
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x2.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image68|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi21_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x4.rst b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x4.rst
index 82eb017..95b4959 100644
--- a/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x4.rst
+++ b/cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_x4.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image71|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi21_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x1.rst b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x1.rst
index 7351b71..02a823f 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x1.rst
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x1.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image56|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi211_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x2.rst b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x2.rst
index f3015ce..d087b9e 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x2.rst
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x2.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image59|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi211_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x4.rst b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x4.rst
index b765896..17450b9 100644
--- a/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x4.rst
+++ b/cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_x4.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image62|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi211_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x1.rst b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x1.rst
index b1237ec..8a4fdc2 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x1.rst
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x1.rst
@@ -61,7 +61,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image92|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi22_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x2.rst b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x2.rst
index 4d630b9..842f267 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x2.rst
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x2.rst
@@ -61,7 +61,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image95|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi22_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x4.rst b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x4.rst
index b2f2967..e7c3342 100644
--- a/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x4.rst
+++ b/cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_x4.rst
@@ -61,7 +61,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image98|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi22_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x1.rst b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x1.rst
index fd24397..c50f31d 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x1.rst
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x1.rst
@@ -63,7 +63,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image74|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi221_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x2.rst b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x2.rst
index 560c3b2..fbf532f 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x2.rst
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x2.rst
@@ -63,7 +63,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image77|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi221_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x4.rst b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x4.rst
index 1255f53..216aafe 100644
--- a/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x4.rst
+++ b/cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_x4.rst
@@ -63,7 +63,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image80|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi221_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x1.rst b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x1.rst
index 30a0f89..b6a3c16 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x1.rst
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x1.rst
@@ -67,7 +67,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image83|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi222_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x2.rst b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x2.rst
index f6c8509..1454f78 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x2.rst
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x2.rst
@@ -67,7 +67,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image86|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi222_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x4.rst b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x4.rst
index 9063b23..77a16ae 100644
--- a/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x4.rst
+++ b/cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_x4.rst
@@ -67,7 +67,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image89|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__aoi222_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x1.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x1.rst
index aeacbf6..bc143e9 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x1.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x1.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image128|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x12.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x12.rst
index 2ff1fe2..f71e676 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x12.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x12.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image122|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_12.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x16.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x16.rst
index 88d0420..4d82bdc 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x16.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x16.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image125|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_16.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x2.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x2.rst
index 748e724..8b837a4 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x2.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x2.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image134|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x20.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x20.rst
index f074de9..073d3cf 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x20.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x20.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image131|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_20.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x3.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x3.rst
index ef0416b..eb987a9 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x3.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x3.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image137|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_3.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x4.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x4.rst
index c7e8ff4..d0da409 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x4.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x4.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image140|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x8.rst b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x8.rst
index 9d667a3..2a8a091 100644
--- a/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x8.rst
+++ b/cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_x8.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image143|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__buf_8.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x1.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x1.rst
index c314318..b348c48 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x1.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x1.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image107|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x12.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x12.rst
index 682f312..1c392e4 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x12.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x12.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image101|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz_12.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x16.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x16.rst
index 2237bcd..2ef4fe0 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x16.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x16.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image104|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz_16.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x2.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x2.rst
index e53ac96..b752826 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x2.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x2.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image110|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x3.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x3.rst
index 3fe3c26..8277476 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x3.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x3.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image113|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz_3.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x4.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x4.rst
index c55c2c8..fa6477c 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x4.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x4.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image116|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x8.rst b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x8.rst
index f589dbf..a22a2bc 100644
--- a/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x8.rst
+++ b/cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_x8.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image119|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__bufz_8.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x1.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x1.rst
index 468981b..329e455 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x1.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x1.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image152|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x12.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x12.rst
index d8458ac..05c842b 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x12.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x12.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image146|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x16.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x16.rst
index a03380f..70c4e9b 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x16.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x16.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image149|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x2.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x2.rst
index 479c707..626ba20 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x2.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x2.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image158|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x20.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x20.rst
index 879c566..fdd5df7 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x20.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x20.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image155|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_20.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x3.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x3.rst
index 439566f..2b1d6c4 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x3.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x3.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image161|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x4.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x4.rst
index 20f5463..0d8886d 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x4.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x4.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image164|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x8.rst b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x8.rst
index 3986b1e..7e47736 100644
--- a/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x8.rst
+++ b/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_x8.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image167|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x1.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x1.rst
index 6ee6c70..be65ecd 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x1.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x1.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image176|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x12.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x12.rst
index 1a3494a..b4760e0 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x12.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x12.rst
@@ -56,7 +56,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image170|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_12.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x16.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x16.rst
index ca415fc..81fc1a2 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x16.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x16.rst
@@ -56,7 +56,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image173|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_16.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x2.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x2.rst
index c6752a0..ef9dcde 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x2.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x2.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image182|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x20.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x20.rst
index cd4d60d..42a1fe2 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x20.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x20.rst
@@ -56,7 +56,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image179|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_20.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x3.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x3.rst
index 0be872f..052a176 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x3.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x3.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image185|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_3.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x4.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x4.rst
index a5d2fe8..2dc12bb 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x4.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x4.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image188|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x8.rst b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x8.rst
index 1853d67..cc20bfd 100644
--- a/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x8.rst
+++ b/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_x8.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image191|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__clkinv_8.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x1.rst b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x1.rst
index dea4dc5..7cce416 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x1.rst
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x1.rst
@@ -51,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image194|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x2.rst b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x2.rst
index 4fe989c..e09fae4 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x2.rst
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x2.rst
@@ -51,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image197|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x4.rst b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x4.rst
index 0719292..7d84674 100644
--- a/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x4.rst
+++ b/cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_x4.rst
@@ -51,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image200|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x1.rst b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x1.rst
index 43c10bc..84c1dc4 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x1.rst
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x1.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image203|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x2.rst b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x2.rst
index 04aeafd..0b7faa2 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x2.rst
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x2.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image206|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x4.rst b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x4.rst
index ddfc3d0..763b840 100644
--- a/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x4.rst
+++ b/cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_x4.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image209|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x1.rst b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x1.rst
index 162fb2f..86688b1 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x1.rst
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x1.rst
@@ -54,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image212|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x2.rst b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x2.rst
index 47b7cf0..496ca51 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x2.rst
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x2.rst
@@ -54,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image215|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x4.rst b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x4.rst
index dacd56e..47b5a51 100644
--- a/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x4.rst
+++ b/cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_x4.rst
@@ -54,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image218|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x1.rst b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x1.rst
index 2378e52..ba32b38 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x1.rst
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x1.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image221|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x2.rst b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x2.rst
index 4d8e9f9..7bf6291 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x2.rst
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x2.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image224|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x4.rst b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x4.rst
index 3bf23c4..68adc6a 100644
--- a/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x4.rst
+++ b/cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_x4.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image227|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffnsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x1.rst b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x1.rst
index fa703cb..8eec3ae 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x1.rst
+++ b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x1.rst
@@ -51,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image230|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x2.rst b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x2.rst
index 4fc64ef..3bc61c4 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x2.rst
+++ b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x2.rst
@@ -51,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image233|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x4.rst b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x4.rst
index accff6a..416e4b7 100644
--- a/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x4.rst
+++ b/cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_x4.rst
@@ -51,7 +51,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image236|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x1.rst b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x1.rst
index f8e1f57..d7c939d 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x1.rst
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x1.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image239|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x2.rst b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x2.rst
index 7e70eed..33e851a 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x2.rst
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x2.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image242|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x4.rst b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x4.rst
index 344f59c..50c7025 100644
--- a/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x4.rst
+++ b/cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_x4.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image245|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x1.rst b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x1.rst
index bd5a216..69403f4 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x1.rst
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x1.rst
@@ -54,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image248|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x2.rst b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x2.rst
index 60ca1cc..6055b03 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x2.rst
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x2.rst
@@ -54,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image251|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x4.rst b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x4.rst
index 642f26a..4a73dc5 100644
--- a/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x4.rst
+++ b/cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_x4.rst
@@ -54,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image254|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x1.rst b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x1.rst
index d34707f..85f0131 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x1.rst
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x1.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image257|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x2.rst b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x2.rst
index dbd556a..ac0ed4b 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x2.rst
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x2.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image260|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x4.rst b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x4.rst
index e65db69..0ef43ff 100644
--- a/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x4.rst
+++ b/cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_x4.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image263|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dffsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x1.rst b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x1.rst
index e5202cc..830e304 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x1.rst
+++ b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x1.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image266|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlya_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x2.rst b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x2.rst
index 54ec686..2cc7408 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x2.rst
+++ b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x2.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image269|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlya_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x4.rst b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x4.rst
index a5e037d..6210ee2 100644
--- a/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x4.rst
+++ b/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_x4.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image272|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlya_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x1.rst b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x1.rst
index 339eea4..c6294ed 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x1.rst
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x1.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image275|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyb_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x2.rst b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x2.rst
index 902cbe1..9585684 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x2.rst
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x2.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image278|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyb_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x4.rst b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x4.rst
index fab2af8..8433081 100644
--- a/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x4.rst
+++ b/cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_x4.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image281|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyb_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x1.rst b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x1.rst
index 8ba644b..2f175fa 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x1.rst
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x1.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image284|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyc_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x2.rst b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x2.rst
index 3027cb1..0563bf2 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x2.rst
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x2.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image287|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyc_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x4.rst b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x4.rst
index 3d28319..3c572fc 100644
--- a/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x4.rst
+++ b/cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_x4.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image290|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyc_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x1.rst b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x1.rst
index 89a9342..d1dfe41 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x1.rst
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x1.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image293|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyd_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x2.rst b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x2.rst
index ecb95ce..bfcd951 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x2.rst
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x2.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image296|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyd_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x4.rst b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x4.rst
index 2a77685..7fe65aa 100644
--- a/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x4.rst
+++ b/cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_x4.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image299|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__dlyd_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.rst b/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.rst
index 213ea36..958390b 100644
--- a/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.rst
+++ b/cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image302|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__endcap.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x1.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x1.rst
index 2408a6e..7efbd2c 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x1.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x1.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image326|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fill_1.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x16.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x16.rst
index be4da59..6a4e029 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x16.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x16.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image323|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fill_16.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x2.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x2.rst
index 7f2b615..71bb766 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x2.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x2.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image329|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fill_2.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x32.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x32.rst
index c0d99ea..b5c44bc 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x32.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x32.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image332|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fill_32.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x4.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x4.rst
index cfd86ae..603a050 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x4.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x4.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image335|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fill_4.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x64.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x64.rst
index 1d016ec..984b19a 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x64.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x64.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image338|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fill_64.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x8.rst b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x8.rst
index aae9551..388eee2 100644
--- a/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x8.rst
+++ b/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_x8.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image341|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fill_8.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x16.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x16.rst
index 35a81ed..d9a690c 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x16.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x16.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image305|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap_16.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x32.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x32.rst
index b789783..6e6f54a 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x32.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x32.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image308|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap_32.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x4.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x4.rst
index 4e033d3..91fdaa8 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x4.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x4.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image311|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap_4.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x64.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x64.rst
index 9fbdd6b..9b41427 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x64.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x64.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image314|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap_64.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x8.rst b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x8.rst
index 9f60428..d6bea28 100644
--- a/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x8.rst
+++ b/cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_x8.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image317|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__fillcap_8.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.rst b/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.rst
index 061cd03..01d0eaf 100644
--- a/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.rst
+++ b/cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.rst
@@ -40,7 +40,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image320|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__filltie.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.rst b/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.rst
index 2d343fc..293507b 100644
--- a/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.rst
+++ b/cells/hold/gf180mcu_fd_sc_mcu7t5v0__hold.rst
@@ -56,7 +56,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image344|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__hold.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x1.rst b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x1.rst
index 293194d..7471508 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x1.rst
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x1.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image347|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtn_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x2.rst b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x2.rst
index 604c5d5..49bcd41 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x2.rst
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x2.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image350|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtn_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x4.rst b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x4.rst
index 5eba836..b4bef33 100644
--- a/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x4.rst
+++ b/cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_x4.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image353|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtn_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x1.rst b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x1.rst
index a55354a..5df4e03 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x1.rst
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x1.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image356|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtp_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x2.rst b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x2.rst
index 4b688e0..27f1c51 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x2.rst
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x2.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image359|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtp_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x4.rst b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x4.rst
index fee812a..f2ee7e3 100644
--- a/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x4.rst
+++ b/cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_x4.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image362|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__icgtp_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x1.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x1.rst
index c1d071d..2318242 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x1.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x1.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image392|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x12.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x12.rst
index 95698aa..b3c942b 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x12.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x12.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image386|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_12.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x16.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x16.rst
index bcfc1da..7b2a4ba 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x16.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x16.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image389|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_16.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x2.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x2.rst
index 770056d..e7d92e4 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x2.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x2.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image398|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x20.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x20.rst
index df2cc99..80b1deb 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x20.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x20.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image395|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_20.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x3.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x3.rst
index 0f9a22d..0a3a485 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x3.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x3.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image401|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_3.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x4.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x4.rst
index b9c70ac..355f20b 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x4.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x4.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image404|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x8.rst b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x8.rst
index f1fdc79..072a5eb 100644
--- a/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x8.rst
+++ b/cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_x8.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image407|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__inv_8.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x1.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x1.rst
index a36f451..789f6d8 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x1.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x1.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image371|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__invz_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x12.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x12.rst
index 5e95bfe..590f76d 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x12.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x12.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image365|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__invz_12.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x16.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x16.rst
index 0249584..bc3f7c7 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x16.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x16.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image368|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__invz_16.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x2.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x2.rst
index 1929eb8..006616c 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x2.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x2.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image374|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__invz_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x3.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x3.rst
index 7300010..03f2cba 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x3.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x3.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image377|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__invz_3.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x4.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x4.rst
index 0305642..b80df8d 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x4.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x4.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image380|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__invz_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x8.rst b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x8.rst
index ec39c3f..d79ade8 100644
--- a/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x8.rst
+++ b/cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_x8.rst
@@ -57,7 +57,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image383|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__invz_8.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x1.rst b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x1.rst
index f56c6b5..3d17464 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x1.rst
+++ b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x1.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image410|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x2.rst b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x2.rst
index 5e5f2f3..0382720 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x2.rst
+++ b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x2.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image413|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x4.rst b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x4.rst
index b002121..21df5fd 100644
--- a/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x4.rst
+++ b/cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_x4.rst
@@ -52,7 +52,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image416|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x1.rst b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x1.rst
index 95b8d7f..bea1e21 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x1.rst
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x1.rst
@@ -53,7 +53,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image419|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latrnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x2.rst b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x2.rst
index 9370be6..f41349d 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x2.rst
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x2.rst
@@ -53,7 +53,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image422|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latrnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x4.rst b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x4.rst
index e3b9d0c..12e4a20 100644
--- a/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x4.rst
+++ b/cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_x4.rst
@@ -53,7 +53,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image425|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latrnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x1.rst b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x1.rst
index 1bc22fe..e89f3b8 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x1.rst
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x1.rst
@@ -55,7 +55,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image428|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latrsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x2.rst b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x2.rst
index 19085e2..14c0dac 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x2.rst
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x2.rst
@@ -55,7 +55,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image431|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latrsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x4.rst b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x4.rst
index 91770ca..1fc5821 100644
--- a/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x4.rst
+++ b/cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_x4.rst
@@ -55,7 +55,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image434|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latrsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x1.rst b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x1.rst
index 57d2e46..cd19de5 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x1.rst
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x1.rst
@@ -53,7 +53,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image437|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x2.rst b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x2.rst
index 3aca247..b25a096 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x2.rst
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x2.rst
@@ -53,7 +53,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image440|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x4.rst b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x4.rst
index b6241ec..c8ef3ff 100644
--- a/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x4.rst
+++ b/cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_x4.rst
@@ -53,7 +53,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image443|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__latsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x1.rst b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x1.rst
index d8c1a14..316dadd 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x1.rst
+++ b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x1.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image446|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__mux2_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x2.rst b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x2.rst
index 4184514..dc2e231 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x2.rst
+++ b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x2.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image449|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__mux2_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x4.rst b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x4.rst
index 37fa665..3072324 100644
--- a/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x4.rst
+++ b/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_x4.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image452|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__mux2_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x1.rst b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x1.rst
index e7bccd2..b02736d 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x1.rst
+++ b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x1.rst
@@ -62,7 +62,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image455|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__mux4_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x2.rst b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x2.rst
index 8472a96..1c0bf98 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x2.rst
+++ b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x2.rst
@@ -62,7 +62,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image458|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__mux4_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x4.rst b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x4.rst
index ff561bd..6cda68a 100644
--- a/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x4.rst
+++ b/cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_x4.rst
@@ -62,7 +62,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image461|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__mux4_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x1.rst b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x1.rst
index e70454d..2b5efb4 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x1.rst
+++ b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x1.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image464|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand2_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x2.rst b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x2.rst
index aa184f3..e242a3a 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x2.rst
+++ b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x2.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image467|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand2_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x4.rst b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x4.rst
index 30a782d..6d6091b 100644
--- a/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x4.rst
+++ b/cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_x4.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image470|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand2_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x1.rst b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x1.rst
index 054d186..34a6a6f 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x1.rst
+++ b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x1.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image473|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand3_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x2.rst b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x2.rst
index deee3b0..3db4be6 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x2.rst
+++ b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x2.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image476|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand3_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x4.rst b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x4.rst
index 7554eda..2560a05 100644
--- a/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x4.rst
+++ b/cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_x4.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image479|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand3_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x1.rst b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x1.rst
index 2865a4f..b06dcc3 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x1.rst
+++ b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x1.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image482|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand4_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x2.rst b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x2.rst
index e7e4c94..c95660b 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x2.rst
+++ b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x2.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image485|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand4_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x4.rst b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x4.rst
index af60ef7..99d8bf1 100644
--- a/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x4.rst
+++ b/cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_x4.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image488|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nand4_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x1.rst b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x1.rst
index 84fbb5d..d9bfb46 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x1.rst
+++ b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x1.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image491|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor2_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x2.rst b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x2.rst
index 1342b18..e2e9efc 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x2.rst
+++ b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x2.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image494|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor2_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x4.rst b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x4.rst
index e549c2c..68d7e08 100644
--- a/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x4.rst
+++ b/cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_x4.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image497|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor2_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x1.rst b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x1.rst
index 9488ca8..49aec6b 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x1.rst
+++ b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x1.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image500|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor3_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x2.rst b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x2.rst
index 5029d85..2666ab5 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x2.rst
+++ b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x2.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image503|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor3_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x4.rst b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x4.rst
index 2e51acd..84c5e38 100644
--- a/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x4.rst
+++ b/cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_x4.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image506|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor3_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x1.rst b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x1.rst
index 3187b02..f04c8be 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x1.rst
+++ b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x1.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image509|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor4_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x2.rst b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x2.rst
index 672c973..027e624 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x2.rst
+++ b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x2.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image512|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor4_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x4.rst b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x4.rst
index 1427131..2a3f315 100644
--- a/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x4.rst
+++ b/cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_x4.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image515|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__nor4_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x1.rst b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x1.rst
index 5959b70..66c830a 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x1.rst
+++ b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x1.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image527|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai21_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x2.rst b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x2.rst
index 9f1666d..cc8997e 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x2.rst
+++ b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x2.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image530|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai21_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x4.rst b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x4.rst
index db84422..0e9952b 100644
--- a/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x4.rst
+++ b/cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_x4.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image533|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai21_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x1.rst b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x1.rst
index e84b42b..aa026f9 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x1.rst
+++ b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x1.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image518|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai211_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x2.rst b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x2.rst
index 08c604a..3888f2c 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x2.rst
+++ b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x2.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image521|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai211_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x4.rst b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x4.rst
index 2e9f205..fbde773 100644
--- a/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x4.rst
+++ b/cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_x4.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image524|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai211_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x1.rst b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x1.rst
index 4d86980..562c8c9 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x1.rst
+++ b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x1.rst
@@ -61,7 +61,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image554|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai22_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x2.rst b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x2.rst
index 16157be..4b2ed18 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x2.rst
+++ b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x2.rst
@@ -61,7 +61,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image557|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai22_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x4.rst b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x4.rst
index 7e67954..6f57a9d 100644
--- a/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x4.rst
+++ b/cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_x4.rst
@@ -61,7 +61,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image560|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai22_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x1.rst b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x1.rst
index a2b545a..3dca5ac 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x1.rst
+++ b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x1.rst
@@ -62,7 +62,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image536|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai221_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x2.rst b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x2.rst
index 6a9feae..9a9c4e2 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x2.rst
+++ b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x2.rst
@@ -62,7 +62,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image539|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai221_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x4.rst b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x4.rst
index ede3255..a27c034 100644
--- a/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x4.rst
+++ b/cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_x4.rst
@@ -62,7 +62,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image542|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai221_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x1.rst b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x1.rst
index c0a9b14..8fc9f0d 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x1.rst
+++ b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x1.rst
@@ -66,7 +66,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image545|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai222_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x2.rst b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x2.rst
index 7059614..b41a5f5 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x2.rst
+++ b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x2.rst
@@ -66,7 +66,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image548|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai222_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x4.rst b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x4.rst
index b1ec638..d383adf 100644
--- a/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x4.rst
+++ b/cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_x4.rst
@@ -66,7 +66,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image551|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai222_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x1.rst b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x1.rst
index 268bf0a..b46419f 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x1.rst
+++ b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x1.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image563|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai31_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x2.rst b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x2.rst
index cd11bc5..66aceb5 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x2.rst
+++ b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x2.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image566|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai31_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x4.rst b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x4.rst
index 9f8914a..a7ea4c7 100644
--- a/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x4.rst
+++ b/cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_x4.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image569|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai31_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x1.rst b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x1.rst
index ff07f8b..d878f58 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x1.rst
+++ b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x1.rst
@@ -63,7 +63,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image572|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai32_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x2.rst b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x2.rst
index cec61d1..16782f7 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x2.rst
+++ b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x2.rst
@@ -63,7 +63,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image575|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai32_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x4.rst b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x4.rst
index f86030b..0b4fb0b 100644
--- a/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x4.rst
+++ b/cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_x4.rst
@@ -63,7 +63,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image578|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai32_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x1.rst b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x1.rst
index 773e429..197e50c 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x1.rst
+++ b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x1.rst
@@ -66,7 +66,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image581|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai33_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x2.rst b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x2.rst
index bb4609a..e1bccf9 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x2.rst
+++ b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x2.rst
@@ -66,7 +66,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image584|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai33_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x4.rst b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x4.rst
index 6b6403a..a21383a 100644
--- a/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x4.rst
+++ b/cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_x4.rst
@@ -66,7 +66,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image587|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__oai33_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x1.rst b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x1.rst
index a3a8bde..34b1c19 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x1.rst
+++ b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x1.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image590|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or2_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x2.rst b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x2.rst
index 8b16164..375668a 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x2.rst
+++ b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x2.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image593|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or2_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x4.rst b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x4.rst
index 9727c71..35c2807 100644
--- a/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x4.rst
+++ b/cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_x4.rst
@@ -58,7 +58,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image596|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or2_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x1.rst b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x1.rst
index c1b1bdf..b002f7c 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x1.rst
+++ b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x1.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image599|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or3_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x2.rst b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x2.rst
index deab681..7daf502 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x2.rst
+++ b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x2.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image602|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or3_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x4.rst b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x4.rst
index 484057d..cdd9471 100644
--- a/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x4.rst
+++ b/cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_x4.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image605|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or3_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x1.rst b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x1.rst
index e5dbe63..7ef44db 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x1.rst
+++ b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x1.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image608|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or4_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x2.rst b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x2.rst
index e4a00ec..34b789f 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x2.rst
+++ b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x2.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image611|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or4_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x4.rst b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x4.rst
index 2ca32ac..d078557 100644
--- a/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x4.rst
+++ b/cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_x4.rst
@@ -60,7 +60,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image614|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__or4_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x1.rst b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x1.rst
index 50cff57..d7e3d6c 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x1.rst
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x1.rst
@@ -53,7 +53,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image617|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x2.rst b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x2.rst
index 493f31a..509cdfd 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x2.rst
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x2.rst
@@ -53,7 +53,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image620|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x4.rst b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x4.rst
index 33ae19f..a2420bd 100644
--- a/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x4.rst
+++ b/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_x4.rst
@@ -53,7 +53,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image623|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x1.rst b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x1.rst
index 3308510..8976d16 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x1.rst
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x1.rst
@@ -54,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image626|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x2.rst b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x2.rst
index 0cc1725..d48318f 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x2.rst
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x2.rst
@@ -54,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image629|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x4.rst b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x4.rst
index f7424dd..80653ba 100644
--- a/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x4.rst
+++ b/cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_x4.rst
@@ -54,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image632|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x1.rst b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x1.rst
index 44a50f5..2a93dd2 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x1.rst
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x1.rst
@@ -56,7 +56,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image635|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x2.rst b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x2.rst
index 0fd106e..15c5284 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x2.rst
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x2.rst
@@ -56,7 +56,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image638|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x4.rst b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x4.rst
index 2a456fa..b133cea 100644
--- a/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x4.rst
+++ b/cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_x4.rst
@@ -56,7 +56,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image641|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x1.rst b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x1.rst
index ef47042..c3e3978 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x1.rst
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x1.rst
@@ -54,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image644|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffsnq_1.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x2.rst b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x2.rst
index 5669455..b7a1944 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x2.rst
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x2.rst
@@ -54,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image647|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffsnq_2.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x4.rst b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x4.rst
index 45ea893..99dedaa 100644
--- a/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x4.rst
+++ b/cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_x4.rst
@@ -54,7 +54,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image650|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4.png
+
| CONSTRAINTS
================== =============== ============= ============
diff --git a/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.rst b/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.rst
index caf4e57..625d4be 100644
--- a/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.rst
+++ b/cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.rst
@@ -55,7 +55,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image653|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__tieh.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.rst b/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.rst
index abd6100..cb11795 100644
--- a/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.rst
+++ b/cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.rst
@@ -55,7 +55,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image656|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__tiel.png
+
| LEAKAGE POWER
================== ==============
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x1.rst b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x1.rst
index 7bbf970..50b65f8 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x1.rst
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x1.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image659|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor2_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x2.rst b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x2.rst
index eb87da3..7b6c8a1 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x2.rst
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x2.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image662|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor2_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x4.rst b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x4.rst
index 1777905..04a91d7 100644
--- a/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x4.rst
+++ b/cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_x4.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image665|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor2_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x1.rst b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x1.rst
index 6432c03..b68148d 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x1.rst
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x1.rst
@@ -63,7 +63,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image668|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor3_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x2.rst b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x2.rst
index a0d8f38..d366c7a 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x2.rst
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x2.rst
@@ -63,7 +63,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image671|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor3_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x4.rst b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x4.rst
index 1810647..9880ac3 100644
--- a/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x4.rst
+++ b/cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_x4.rst
@@ -63,7 +63,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image674|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xnor3_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x1.rst b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x1.rst
index fdf4df9..2012f90 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x1.rst
+++ b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x1.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image677|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xor2_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x2.rst b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x2.rst
index 34690dd..c1ac17d 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x2.rst
+++ b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x2.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image680|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xor2_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x4.rst b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x4.rst
index da8e9d7..817e30f 100644
--- a/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x4.rst
+++ b/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_x4.rst
@@ -59,7 +59,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image683|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xor2_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x1.rst b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x1.rst
index 0048dd6..9ee346b 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x1.rst
+++ b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x1.rst
@@ -63,7 +63,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image686|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xor3_1.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x2.rst b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x2.rst
index e622af7..c3d8fe8 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x2.rst
+++ b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x2.rst
@@ -63,7 +63,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image689|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xor3_2.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
diff --git a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x4.rst b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x4.rst
index 086924b..8a9d6cd 100644
--- a/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x4.rst
+++ b/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_x4.rst
@@ -63,7 +63,9 @@
|
| FUNCTIONAL SCHEMATIC
-| |image692|
+
+.. image:: gf180mcu_fd_sc_mcu7t5v0__xor3_4.png
+
| PIN CAPACITANCE (pf)
======= ======== ====================
