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physical_verification
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design_manual
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drm_01.rst
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1.0
Purpose
===========
This
document provides topological layout rules to generate masks
for
0.18
ยต
m
**
1.8V
/
6V
CMOS
**
and
**
1.8V
/
6V
/
30V
/
35V
LDMOS dual
-
gate high voltage process
in
GLOBALFOUNDRIES
.**
