| set ::env(DESIGN_NAME) "raven_soc" | |
| set ::env(VERILOG_FILES) "./designs/raven_soc/src/raven_soc.v" | |
| set ::env(CLOCK_PERIOD) "10" | |
| # which clock port ?? | |
| set ::env(CLOCK_PORT) "ext_clk" | |
| set ::env(FP_CORE_MARGIN) 3.36 | |
| set ::env(SYNTH_STRAT) 2 | |
| set ::env(SYNTH_MAX_FANOUT) 6 | |
| set ::env(PL_TARGET_DENSITY) 0.35 | |
| set ::env(GLB_RT_ADJUSTMENT) 0.15 | |
| set ::env(PDK_VARIANT) scs8ms | |