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foss-eda-tools / efabless / openlane / 9b2c6f60d58368b5f7a2938643c7812bb381dd90 / . / designs
tree: fbafd2e69dff14166b0997291ccb7ac75720f4a2 [path history] [tgz]
  1. aes/
  2. aes128/
  3. aes192/
  4. aes256/
  5. aes_core/
  6. APU/
  7. blabla/
  8. chacha/
  9. cic_decimator/
  10. cordic/
  11. cpu6502/
  12. CPU_CV/
  13. des/
  14. des3/
  15. genericfir/
  16. ksa/
  17. md5/
  18. picorv32a/
  19. point_add/
  20. point_scalar_mult/
  21. PPU/
  22. r8051/
  23. raven_soc/
  24. salsa20/
  25. serv_top/
  26. sha3/
  27. sha512/
  28. spm/
  29. sub86/
  30. TEA/
  31. tv80/
  32. usb/
  33. usbf_device/
  34. wb_conbus_top/
  35. xtea/
  36. y_dct/
  37. y_huff/
  38. zipdiv/
  39. .gitignore
  40. designs_results.md
  41. README.md
designs/README.md

Variables information

This page describes configuration variables and list the defaults for skywater130 pdk.

Required variables

VariableDescription
DESIGN_NAMEThe name of the top level module of the design
VERILOG_FILESThe path of the design's verilog files
CLOCK_PERIODThe clock period for the design in ns
CLOCK_PORTThe name of the design's clock port

Optional variables

These variables are optional that can be specified in the design configuration file.

Synthesis

VariableDescription
LIB_SYNTHThe library used for synthesis by yosys.
(Default: ./pdks/skywater130/scc8lp/scs8lp_ss_1.65v_-40C.lib)
SYNTH_DRIVING_CELLThe cell to drive the input ports.
(Default: scs8lp_inv_8)
SYNTH_DRIVING_CELL_PINThe name of the SYNTH_DRIVING_CELL output pin.
(Default: Y)
SYNTH_CAP_LOADThe capacitive load on the output ports in femtofarads.
(Default: 24.36 ff)
SYNTH_MAX_FANOUTThe max load that the output ports can drive.
(Default: 5 cells)
SYNTH_MAX_TRANSThe max transition time (slew) from high to low or low to high on cell inputs in ns. Used in synthesis
(Default: Calculated at runtime as 10% of the provided clock period)
SYNTH_STRATEGYStratgies for abc logic synthesis and technology mapping
Possible values are 0, 1 (delay), 2, and 3 (area)
(Default: 2)
SYNTH_BUFFERINGEnables abc buffering
Enabled = 1, Disabled = 0
(Default: 1)
LIB_MINLibrary used for min delay calculation during STA.
(Default:./pdks/skywater130/scc8lp/scs8lp_ss_1.65v_-40C.lib)
LIB_MAXLibrary used for max delay calculation during STA.
(Default:./pdks/skywater130/scc8lp/scs8lp_ff_1.65v_-40C.lib)
LIB_TYPICALLibrary used for typical delay calculation during STA.
(Default./pdks/skywater130/scc8lp/scs8lp_ss_1.65v_-40C.lib:)

Floorplanning

VariableDescription
FP_CORE_UTILThe core utilization percentage.
(Default: 50 percent)
FP_ASPECT_RATIOThe core's aspect ratio (height / width).
(Default: 1)
FP_CORE_MARGINThe length of the margin surrounding the core area.
(Default: 3.36 microns)
FP_IO_HMETALThe metal layer on which to place the io pins horizontally (top and bottom of the die).
(Default: 3)
FP_IO_VMETALThe metal layer on which to place the io pins vertically (sides of the die)
(Default: 2)
FP_WELLTAP_CELLThe name of the welltap cell during welltap insertion.
(Default: scs8lp_tap_1)
FP_ENDCAP_CELLThe name of the endcap cell during endcap insertion.
(Default: scs8lp_decap_3)
FP_PDN_VOFFSETThe offset of the vertical power stripes on the metal layer 4 in the power distribution network
(Default: 16.32)
FP_PDN_VPITCHThe pitch of the vertical power stripes on the metal layer 4 in the power distribution network
(Default: 153.6)
FP_PDN_HOFFSETThe offset of the horizontal power stripes on the metal layer 5 in the power distribution network
(Default: 16.65)
FP_PDN_HPITCHThe pitch of the horizontal power stripes on the metal layer 5 in the power distribution network
(Default: 153.18)

Placement

VariableDescription
PL_TARGET_DENSITYThe desired placement density of cells. It reflects how spread the cells would be on the core area. 1 = closely dense. 0 = widely spread
(Default: 0.4)
PL_TIME_DIRVENSpecifies whether the placer should use time driven placement. 0 = false, 1 = true
(Default: 0)
PL_LIBSpecifies the library for time driven placement
(Default: LIB_TYPICAL)

CTS

VariableDescription
CTS_TARGET_SKEWThe target clock skew in picoseconds.
(Default: 20 ps)
CTS_ROOT_BUFFERThe name of cell inserted at the root of the clock tree.
(Default: scs8lp_clkbuf_16)
CTS_TECH_DIRThe directory of look-up-tables for tirtonCTS.
(Default: ./pdks/skywater130/cts_lut_common)
CTS_TOLERANCEan integer value that represents a tradeoff of QoR and runtime. Higher values will produce smaller runtime but worse QoR
(Default: 100)

Routing

VariableDescription
GLB_RT_MAXLAYERThe number of highest layer to be used in routing.
(Default: 6)
GLB_RT_ADJUSTMENTReduction in the routing capacity of the edges between the cells in the global routing graph. Values range from 0 to 1.
1 = most reduction, 0 = least reduction
(Default: 0.15)
GLB_RT_LI1_ADJUSTMENTReduction in the routing capacity of the edges between the cells in the global routing graph but specific to li1 layer in skywater130. Values range from 0 to 1
(Default: 0)
GLB_RT_MET1_ADJUSTMENTReduction in the routing capacity of the edges between the cells in the global routing graph but specific to met1 in skywater130. Values range from 0 to 1
(Default: 0)

Misc

VariableDescription
PDKSpecifies the process design kit (pdk).
(Default: skywater130 )
PDK_VARIANTSpecifies the process design kit (pdk) variant.
(Default: scs8lp )
CELL_PADCell padding; increases the width of cells.
(Default: 0.96 microns -- 2 sites)

Available Designs

This repo has several designs that were used to validate the flow. The results of running the flow on some of these designs can be found here

Flow control

VariableDescription
RUN_ROUTING_DETAILEDEnables detailed routing. 1 = Enabled, 0 = Disabled
(Default: 1)
RUN_MAGICEnables running magic and GDSII streaming.1 = Enabled, 0 = Disabled
(Default: 0)
CLOCK_TREE_SYNTHEnables cts.1 = Enabled, 0 = Disabled
(Default: 0)
FILL_INSERTIONEnables fill cells insertion after cts (if enabled) .1 = Enabled, 0 = Disabled
(Default: 0)