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#----------------------------------------------------------
# Copyright (c) 2019 R. Timothy Edwards
# Revisions: See below
#
# This file is an Open Source foundry process describing
# the SkyWater S8 hybrid 0.18um / 0.13um fabrication
# process. The file may be distributed under the terms
# of the (Apache 2.0(?)) license agreement.
#
#----------------------------------------------------------
# This file is designed to be used with magic versions 8.2
# or newer.
#----------------------------------------------------------
tech
format 34
EFS8A
end
version
version 20191024
description "SkyWater S8: PRE ALPHA Vendor Open Source rules and DRC"
end
#----------------------------------------------------------
# Status: 3/17/19: s8.tech created from xh018.tech
#
# Status: 3/20/19: Rev 0 (pre-alpha):
# Work in progress. Converted from original techfile to S8
# with all sections updated with as much information as could
# be immediately gleaned from the documentation. Cifinput and
# DRC sections have been checked against one standard cell
# library.
#--------------------------------------------------------------
#--------------------------------------------------------------
# Supported device types
#--------------------------------------------------------------
# device name magic ID layer description
#-------------------------------------------------------------
# nshort nfet standard nFET
# nlowvt nfetlvt low Vt nFET
# sonos_p/e nsonos SONOS nFET
# pshort pfet standard pFET
# plowvt pfetlvt low Vt pFET
# phighvt pfethvt high Vt pFET
# ntvnative --- native nFET
# phv mvpfet thickox pFET
# nhv mvnfet thickox nFET
# nhvnative mvnnfet thickox native nFET
# ndiode ndiode n+ diff diode
# ndiode_h mvndiode thickox n+ diff diode
# pdiode pdiode p+ diff diode
# pdiode_h mvpdiode thickox p+ diff diode
# ndiode_native nndiode diode with nndiff
# ndiode_lvt ndiodelvt low Vt n+ diff diode
# pdiode_lvt pdiodelvt low Vt p+ diff diode
# pdiode_hvt pdiodehvt high Vt p+ diff diode
# nwdiode --- nwell diode
# dnwdiode_psub --- deep nwell diode to substrate
# dnwdiode_pw --- deep nwell diode to pwell
# xcmimc1 mimcap MiM cap 1st plate
# xcmimc2 mimcap2 MiM cap 2nd plate
# mrdn rdn n+ diff resistor
# mrdn_hv mvrdn thickox n+ diff resistor
# mrdp rdp p+ diff resistor
# mrdp_hv mvrdp thickox p+ diff resistor
# mrl1 rli local interconnect resistor
# mrp1 npres n+ poly resistor
# xhrpoly_* ppres (*) p+ poly resistor
# xcnwvc varactor varactor (low Vt?)
# xcnwvc2 varactorhvt high Vt varactor
# xchnwc mvvaractor thickox varactor
# xpwres rpw pwell resistor (in deep nwell)
#
# (*) Note that ppres may extract into some generic type
# called "xhrpoly", but only specific sizes of xhrpoly are
# allowed, and these are created from fixed layouts like the
# types below.
#
# To avoid creating a large number of types, a few ID layers are
# used in conjunction with standard devices types: "lvt" for
# low threshold voltage, and "hvt" for high threshold voltage.
# "dnwell" is used as an identifier layer where appropriate.
# Layer HVI (thick oxide) is treated differently, and types
# "mv*" are defined where thick oxide is required.
#
#-------------------------------------------------------------
# The following devices are not extracted but are represented
# only by script-generated subcells in the PDK.
#-------------------------------------------------------------
# nshortesd ESD nFET
# nhvesd ESD thickox nFET
# nhvnativeesd ESD native nFET
# phvesd ESD thickox pFET
# fnpass flash nFET device
# xchvnwc floating gate varactor
# npnpar1x* parasitic NPN
# npn_1x1_2p0_hv thickox gated parasitic NPN
# pnppar parasitic PNP
# pnppar5x parasitic PNP
# xesd_ndiode_h_*** ESD n+ diode
# xesd_pdiode_h_*** ESD p+ diode
# reslocsub local substrate island indicator
# xcmvpp Vpp cap
# xcmvpp_2 Vpp cap
# xcmvpp_* Vpp cap
# xcmvpp* Vpp cap
# balun balun inductor
# ind4 inductor
# fuse metal fuse device
#--------------------------------------------------------------
#-----------------------------------------------------
# Tile planes
#-----------------------------------------------------
planes
dwell,dw
well,w
active,a
locali,li1,li
metal1,m1
metal2,m2
metal3,m3
metal4,m4
metal5,m5
metali,mi
block,b
comment,c
end
#-----------------------------------------------------
# Tile types
#-----------------------------------------------------
types
# Deep nwell
dwell dnwell,dnw
# Wells
well nwell,nw
-well pwell,pw
-well rpw,rpwell
-well obswell
# Transistors
active nmos,ntransistor,nfet
active pmos,ptransistor,pfet
-active nnmos,nntransistor
active mvnmos,mvntransistor,mvnfet
active mvpmos,mvptransistor,mvpfet
-active mvnnmos,mvnntransistor,mvnnfet,nnfet
-active varactor,varact,var
-active mvvaractor,mvvaract,mvvar
-active pmoslvt,pfetlvt
-active pmoshvt,pfethvt
-active nmoslvt,nfetlvt
-active varactorhvt,varacthvt,varhvt
-active nsonos,sonos
# Diffusions
active ndiff,ndiffusion,ndif
active pdiff,pdiffusion,pdif
-active mvndiff,mvndiffusion,mvndif
-active mvpdiff,mvpdiffusion,mvpdif
active ndiffc,ndcontact,ndc
active pdiffc,pdcontact,pdc
-active mvndiffc,mvndcontact,mvndc
-active mvpdiffc,mvpdcontact,mvpdc
active psubdiff,psubstratepdiff,ppdiff,ppd,psd
active nsubdiff,nsubstratendiff,nndiff,nnd,nsd
-active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd
-active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd
active psubdiffcont,psubstratepcontact,psc
active nsubdiffcont,nsubstratencontact,nsc
-active mvpsubdiffcont,mvpsubstratepcontact,mvpsc
-active mvnsubdiffcont,mvnsubstratencontact,mvnsc
-active obsactive
-active mvobsactive
# Poly
active poly,p,polysilicon
active polycont,pc,pcontact,polycut,polyc
# Resistors
-active npolyres,npres,mrp1
-active ppolyres,ppres,xhrpoly
-active ndiffres,rnd,rdn,rndiff
-active pdiffres,rpd,rdp,rpdiff
-active mvndiffres,mvrnd,mvrdn,mvrndiff
-active mvpdiffres,mvrpd,mvrdp,mvrpdiff
# Diodes
-active pdiode,pdi
-active ndiode,ndi
-active nndiode,nndi
-active pdiodec,pdic
-active ndiodec,ndic
-active nndiodec,nndic
-active mvpdiode,mvpdi
-active mvndiode,mvndi
-active mvpdiodec,mvpdic
-active mvndiodec,mvndic
-active pdiodelvt,pdilvt
-active pdiodehvt,pdihvt
-active ndiodelvt,ndilvt
-active pdiodelvtc,pdilvtc
-active pdiodehvtc,pdihvtc
-active ndiodelvtc,ndilvtc
# Local Interconnect
locali locali,li1,li
-locali rlocali,rli1,rli
locali viali,vial,lic,licon,m1c,v0
-locali obsli1,obsli
-locali obsli1c,obslic,obslicon
# Metal 1
metal1 metal1,m1,met1
-metal1 rmetal1,rm1,rmet1
metal1 via1,m2contact,m2cut,m2c,via,v,v1
-metal1 obsm1
-metal1 padl
# Metal 2
metal2 metal2,m2,met2
-metal2 rmetal2,rm2,rmet2
metal2 via2,m3contact,m3cut,m3c,v2
-metal2 obsm2
# Metal 3
metal3 metal3,m3,met3
-metal3 rmetal3,rm3,rmet3
-metal3 obsm3
metal3 via3,v3
-metal2 mimcapcontact,mimcapc,mimcc,capmc
-metal3 mimcap,mim,capm
# Metal 4
metal4 metal4,m4,met4
-metal4 rmetal4,rm4,rmet4
-metal4 obsm4
metal4 via4,v4
-metal3 mimcap2contact,mimcap2c,mim2cc,capm2c
-metal4 mimcap2,mim2,capm2
# Metal 5
metal5 metal5,m5,met5
-metal5 rm5,rmetal5,rmet5
-metal5 obsm5
-metali metalrdl,mrdl,metrdl
# Miscellaneous
-block glass
-block fillblock
-comment comment
-comment obscomment
end
#-----------------------------------------------------
# Magic contact types
#-----------------------------------------------------
contact
pc poly locali
ndc ndiff locali
pdc pdiff locali
nsc nsd locali
psc psd locali
ndic ndiode locali
nndic nndiode locali
pdic pdiode locali
mvndc mvndiff locali
mvpdc mvpdiff locali
mvnsc mvnsd locali
mvpsc mvpsd locali
mvndic mvndiode locali
mvpdic mvpdiode locali
lic locali metal1
via1 metal1 metal2
via2 metal2 metal3
mimcc metal2 mimcap
mim2cc metal3 mimcap2
via3 metal3 metal4
via4 metal4 metal5
stackable
padl m1 m2 m3 m4 m5 glass
end
#-----------------------------------------------------
# Layer aliases
#-----------------------------------------------------
aliases
allwellplane nwell
allnwell nwell,obswell
allnfets nfet,mvnfet,mvnnfet,nfetlvt,nsonos
allpfets pfet,mvpfet,pfethvt,pfetlvt
allfets allnfets,allpfets,varactor,mvvaractor,varhvt
allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
allnactive allnactivenonfet,allnfets
allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
allnactivetap *nsd,*mvnsd
allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
allpactive allpactivenonfet,allpfets
allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
allpactivetap *psd,*mvpsd
allactivenonfet allnactivenonfet,allpactivenonfet
allactive allactivenonfet,allfets
allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,nfetlvt,nsonos
allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,pfetlvt,pfethvt
alldifflv allndifflv,allpdifflv
allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet
alldiffmv allndiffmv,allpdiffmv
allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
alldiffnonfet alldifflvnonfet,alldiffmvnonfet
alldiff alldifflv,alldiffmv
allpolyres mrp1,xhrpoly
allsblkgennocap_0_4um mrp1,xhrpoly,rnd,rpd,mvrdn,mvrdp
allpolynonfet *poly,allpolyres
allpolynonres *poly,allfets
allpoly allpolynonfet,allfets
allpolynoncap *poly,allfets,allpolyres
allndiffcontlv ndc,nsc,ndic,ndilvtc
allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
allndiffcontmv mvndc,mvnsc,mvndic
allpdiffcontmv mvpdc,mvpsc,mvpdic
allndiffcont allndiffcontlv,allndiffcontmv
allpdiffcont allpdiffcontlv,allpdiffcontmv
alldiffcontlv allndiffcontlv,allpdiffcontlv
alldiffcontmv allndiffcontmv,allpdiffcontmv
alldiffcont alldiffcontlv,alldiffcontmv
allcont alldiffcont,pc
allres allpolyres,allactiveres
allli *locali,rli
allm1 *m1,rm1
allm2 *m2,rm2
allm3 *m3,rm3
allm4 *m4,rm4
allm5 *m5,rm5
allpad padl
psub pwell
end
#-----------------------------------------------------
# Layer drawing styles
#-----------------------------------------------------
styles
styletype mos
dnwell cwell
nwell nwell
pwell pwell
rpwell pwell ptransistor_stripes
ndiff ndiffusion
pdiff pdiffusion
nsd ndiff_in_nwell
psd pdiff_in_pwell
nfet ntransistor ntransistor_stripes
pfet ptransistor ptransistor_stripes
var polysilicon ndiff_in_nwell
ndc ndiffusion metal1 contact_X'es
pdc pdiffusion metal1 contact_X'es
nsc ndiff_in_nwell metal1 contact_X'es
psc pdiff_in_pwell metal1 contact_X'es
pfetlvt ptransistor ptransistor_stripes implant1
pfethvt ptransistor ptransistor_stripes implant2
nfetlvt ntransistor ntransistor_stripes implant1
nsonos ntransistor implant3
mvndiff ndiffusion hvndiff_mask
mvpdiff pdiffusion hvpdiff_mask
mvnsd ndiff_in_nwell hvndiff_mask
mvpsd pdiff_in_pwell hvpdiff_mask
mvnfet ntransistor ntransistor_stripes hvndiff_mask
mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
mvpfet ptransistor ptransistor_stripes
mvvar polysilicon ndiff_in_nwell hvndiff_mask
mvndc ndiffusion metal1 contact_X'es hvndiff_mask
mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
poly polysilicon
pc polysilicon metal1 contact_X'es
npolyres polysilicon silicide_block nselect2
ppolyres polysilicon silicide_block pselect2
pdiode pdiffusion pselect2
ndiode ndiffusion nselect2
pdiodec pdiffusion pselect2 metal1 contact_X'es
ndiodec ndiffusion nselect2 metal1 contact_X'es
ndiodelvt ndiffusion nselect2 implant1
pdiodelvt pdiffusion pselect2 implant1
pdiodehvt pdiffusion pselect2 implant2
mvpdiode pdiffusion pselect2 hvpdiff_mask
mvndiode ndiffusion nselect2 hvndiff_mask
nndiode ndiff_in_nwell nselect2 hvndiff_mask
mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
locali metal1
rli metal1 poly_resist_stripes
lic metal1 metal2 via1arrow
obsli metal1
metal1 metal2
rm1 metal2 poly_resist_stripes
obsm1 metal2
m2c metal2 metal3 via2arrow
metal2 metal3
rm2 metal3 poly_resist_stripes
obsm2 metal3
m3c metal3 metal4 via3alt
metal3 metal4
rm3 metal4 poly_resist_stripes
obsm3 metal4
mimcap metal3 metal2
mimcc metal3 contact_X'es mems
mimcap2 metal4 metal3
mim2cc metal4 contact_X'es mems
via3 metal4 metal5 via4
metal4 metal5
rm4 metal5 poly_resist_stripes
obsm4 metal5
via4 metal5 metal6 via5
metal5 metal6
rm5 metal6 poly_resist_stripes
obsm5 metal6
metalrdl metal7
glass overglass
mrp1 poly_resist poly_resist_stripes
xhrpoly poly_resist silicide_block
ndiffres ndiffusion ndop_stripes
pdiffres pdiffusion pdop_stripes
mvndiffres ndiffusion hvndiff_mask ndop_stripes
mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
comment comment
error_p error_waffle
error_s error_waffle
error_ps error_waffle
fillblock cwell
obswell cwell
obsactive implant4
padl metal6 via6 overglass
magnet substrate_field_implant
rotate via3alt
fence via5
end
#-----------------------------------------------------
# Special paint/erase rules
#-----------------------------------------------------
compose
compose nfet poly ndiff
compose pfet poly pdiff
compose var poly nsd
compose mvnfet poly mvndiff
compose mvpfet poly mvpdiff
compose mvvar poly mvnsd
paint mimcap m3 mimcap
paint mimcapc m3 mimcapc
paint mimcap2 m4 mimcap2
paint mimcap2c m4 mimcap2c
paint ndc nwell pdc
paint nfet nwell pfet
paint ndiff nwell pdiff
paint psd nwell nsd
paint psc nwell nsc
paint pdc pwell ndc
paint pfet pwell nfet
paint pdiff pwell ndiff
paint nsd pwell psd
paint nsc pwell psc
paint m4 obsm4 m4
paint m5 obsm5 m5
end
#-----------------------------------------------------
# Electrical connectivity
#-----------------------------------------------------
connect
*nwell,*nsd,*mvnsd *nwell,*nsd,*mvnsd
pwell,*psd,*mvpsd pwell,*psd,*mvpsd
*li *li
*m1 *m1
*m2 *m2
*m3 *m3
*m4 *m4
*m5 *m5
*mimcap *mimcap
*mimcap2 *mimcap2
allnactivenonfet allnactivenonfet
allpactivenonfet allpactivenonfet
*poly,allfets *poly,allfets
# RDL connects to m5 (i.e., padl) through glass cut
glass metrdl
end
#-----------------------------------------------------
# CIF/GDS output layer definitions
#-----------------------------------------------------
# NOTE: All values in this section MUST be multiples of 25
# or else magic will scale below the allowed layout grid size
cifoutput
#----------------------------------------------------------------
style gdsii
# NOTE: This section is used for actual GDS output
#----------------------------------------------------------------
scalefactor 10 nanometers
options calma-permissive-labels
gridlimit 5
#----------------------------------------------------------------
# DNWELL
#----------------------------------------------------------------
layer DNWELL dnwell
calma 64 18
layer PWRES rpw
and dnwell
calma 64 13
#----------------------------------------------------------------
# NWELL
#----------------------------------------------------------------
layer NWELL allnwell
calma 64 20
templayer nwell_grow allnwell
grow 430
#----------------------------------------------------------------
# DIFF
#----------------------------------------------------------------
layer DIFF allnactivenontap,allpactivenontap
labels allnactivenontap,allpactivenontap
calma 65 20
#----------------------------------------------------------------
# TAP
#----------------------------------------------------------------
layer TAP allnactivetap,allpactivetap
labels allnactivetap,allpactivetap
calma 65 44
#----------------------------------------------------------------
# PPLUS, NPLUS (PSDM, NSDM)
#----------------------------------------------------------------
layer PPLUS allpactivetap
grow 180
calma 94 20
layer PPLUS allpactivenontap
grow 180
calma 94 20
layer NPLUS allnactivetap
grow 180
calma 93 44
layer NPLUS allnactivenontap
grow 180
calma 93 44
layer PPLUS
bloat-all xhrpoly *poly
grow 110
calma 94 20
#----------------------------------------------------------------
# LVTN
#----------------------------------------------------------------
layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,pdiodelvt,ndiodelvt,nndiode
grow 180
calma 125 44
#----------------------------------------------------------------
# HVTP
#----------------------------------------------------------------
layer HVTP pfethvt,varhvt,pdiodehvt
grow 180
calma 78 44
#----------------------------------------------------------------
# SONOS
#----------------------------------------------------------------
layer SONOS nsonos
grow 100
calma 80 20
#----------------------------------------------------------------
# RPM
#----------------------------------------------------------------
layer RPM
bloat-all xhrpoly *poly
grow 200
calma 86 20
#----------------------------------------------------------------
# POLY
#----------------------------------------------------------------
layer POLY allpoly
calma 66 20
layer POLYTXT
labels allpoly noport
calma 66 16
layer POLYPIN
labels allpoly port
calma 66 5
#----------------------------------------------------------------
# THKOX (HVI)
#----------------------------------------------------------------
layer THKOX alldiffmv,mvvar
grow 3600
shrink 3280
bloat-all alldiffmv nwell
calma 75 20
#----------------------------------------------------------------
# CONT (LICON)
#----------------------------------------------------------------
layer CONT allcont
squares-grid 0 170 170
calma 66 44
#----------------------------------------------------------------
# NPC (Nitride poly cut)
# surrounds CONT (LICON) on poly only (i.e., pc)
#----------------------------------------------------------------
layer NPC pc
squares-grid 0 170 170
grow 100
calma 95 20
# NPC is also generated around xhrpoly resistors
layer NPC
bloat-all xhrpoly *poly
grow 95
calma 95 20
#----------------------------------------------------------------
# Device markers
#----------------------------------------------------------------
layer DIFFRES rdn,mvrdn,rdp,mvrdp
calma 65 13
layer POLYRES mrp1,xhrpoly
calma 66 13
layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
# To be done: Expand to include anode, cathode, and guard ring
calma 81 23
#----------------------------------------------------------------
# LI
#----------------------------------------------------------------
layer LI allli
calma 67 20
#----------------------------------------------------------------
# MCON
#----------------------------------------------------------------
layer MCON lic
squares-grid 0 170 190
calma 67 44
#----------------------------------------------------------------
# MET1
#----------------------------------------------------------------
layer MET1 allm1
calma 68 20
layer MET1TXT
labels allm1 noport
calma 68 16
layer MET1PIN
labels allm1 port
calma 68 5
#----------------------------------------------------------------
# VIA1
#----------------------------------------------------------------
layer VIA1 via1
squares-grid 55 150 170
calma 68 44
#----------------------------------------------------------------
# MET2
#----------------------------------------------------------------
layer MET2 allm2
calma 69 20
layer MET2TXT
labels allm2 noport
calma 69 16
layer MET2PIN
labels allm2 port
calma 69 5
#----------------------------------------------------------------
# VIA2
#----------------------------------------------------------------
layer VIA2 via2
squares-grid 40 200 200
calma 69 44
#----------------------------------------------------------------
# MET3
#----------------------------------------------------------------
layer MET3 allm3
calma 70 20
layer MET3TXT
labels allm3 noport
calma 70 5
layer MET3PIN
labels allm3 port
calma 70 16
#----------------------------------------------------------------
# VIA3
#----------------------------------------------------------------
layer VIA3 via3
squares-grid 60 200 200
calma 70 44
#----------------------------------------------------------------
# MET4
#----------------------------------------------------------------
layer MET4 allm4
labels allm4 noport
calma 71 20
layer MET4TXT
labels allm4 noport
calma 71 16
layer MET4PIN
labels allm4 port
calma 71 5
#----------------------------------------------------------------
# VIA4
#----------------------------------------------------------------
layer VIA4 via4
squares-grid 190 800 800
calma 71 44
#----------------------------------------------------------------
# MET5
#----------------------------------------------------------------
layer MET5 allm5
calma 72 20
layer MET5TXT
labels allm5 noport
calma 50 16
layer MET5PIN
labels allm5 port
calma 50 5
#----------------------------------------------------------------
# RDL
#----------------------------------------------------------------
layer RDL metrdl
calma 74 20
layer RDLTXT
labels metrdl noport
calma 74 16
layer RDLPIN
labels metrdl port
calma 74 5
#----------------------------------------------------------------
# GLASS
#----------------------------------------------------------------
layer GLASS glass
calma 76 20
#----------------------------------------------------------------
# BOUND
#----------------------------------------------------------------
layer BOUND
boundary
calma 81 4
#----------------------------------------------------------------
# CAPM
#----------------------------------------------------------------
layer CAPM *mimcap
labels mimcap
calma 89 44
layer CAPM2 *mimcap2
labels mimcap2
calma 97 44
#----------------------------------------------------------------
# FILLBLOCK
#----------------------------------------------------------------
layer FILLOBSM1 fillblock
calma 62 24
layer FILLOBSM2 fillblock
calma 105 52
layer FILLOBSM3 fillblock
calma 107 24
layer FILLOBSM4 fillblock
calma 112 4
#----------------------------------------------------------------
style drc
#----------------------------------------------------------------
# NOTE: This style is used for DRC only, not for GDS output
#----------------------------------------------------------------
scalefactor 10 nanometers
options calma-permissive-labels
# Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
templayer dnwell_shrink dnwell
shrink 1030
templayer nwell_missing dnwell
grow 400
and-not dnwell_shrink
and-not nwell
# SONOS nFET devices must be in deep nwell
templayer dnwell_missing nsonos
and-not dnwell
templayer ptap_reach *psd,*mvpsd
grow 1600
and-not allnwell
grow 1600
and-not allnwell
grow 1600
and-not allnwell
grow 1600
and-not allnwell
grow 1600
and-not allnwell
grow 1600
and-not allnwell
grow 1600
and-not allnwell
grow 800
templayer ptap_missing *ndiff,*mvndiff
and-not ptap_reach
templayer ntap_reach *nsd
grow 1600
and allnwell
grow 1600
and allnwell
grow 1600
and allnwell
grow 1600
and allnwell
grow 800
and allnwell
templayer mvntap_reach *mvnsd
grow 1600
and allnwell
grow 1600
and allnwell
grow 1600
and allnwell
grow 1600
and allnwell
grow 800
and allnwell
templayer mvptap_reach *mvpsd
grow 1600
and-not allnwell
grow 1600
and-not allnwell
grow 1600
and-not allnwell
grow 1600
and-not allnwell
grow 800
and-not allnwell
templayer ntap_missing *pdiff
and-not ntap_reach
templayer mvntap_missing *mvpdiff
and-not mvntap_reach
templayer mvptap_missing *mvndiff
and-not mvptap_reach
#----------------------------------------------------------------
style metfill
#----------------------------------------------------------------
# NOTE: This section used for metal filling output
# by a sequence of cif paint commands
#----------------------------------------------------------------
scalefactor 10 nanometers
options calma-permissive-labels
gridlimit 5
#----------------------------------------------------------------
# MET1 FILL
#----------------------------------------------------------------
templayer slots_m1
bbox top
slots 32000 1150 1650 32000 13350 14650
templayer slots_m1
bbox top
slots 33400 1150 1650 46000 13350 14650
templayer obstruct_m1 allm1,allpad,allngf
grow 800
shrink 500
grow 500
layer met1fill slots_m1
and-not obstruct_m1
shrink 550
grow 550
#----------------------------------------------------------------
# MET2 FILL
#----------------------------------------------------------------
templayer slots_m2
bbox top
slots 32000 13350 14650 32000 1150 1650
templayer slots_m2
bbox top
slots 46000 13350 14650 33400 1150 1650
templayer obstruct_m2 allm2,allpad,allngf
grow 800
shrink 500
grow 500
layer met2fill slots_m2
and-not obstruct_m2
shrink 550
grow 550
#----------------------------------------------------------------
# MET3 FILL
#----------------------------------------------------------------
templayer slots_m3
bbox top
slots 33400 1150 1650 32000 13350 14650
templayer slots_m3
bbox top
slots 32000 1150 1650 46000 13350 14650
templayer obstruct_m3 allm3,allpad,allngf
grow 800
shrink 500
grow 500
layer met3fill slots_m3
and-not obstruct_m3
shrink 550
grow 550
#----------------------------------------------------------------
# MET4 FILL
#----------------------------------------------------------------
templayer slots_m4
bbox top
slots 32000 11500 2500 32000 4500 2500
templayer obstruct_m4 allm4,allpad,allngf
grow 500
shrink 500
grow 500
layer met4fill slots_m4
and-not obstruct_m4
shrink 220
grow 220
#----------------------------------------------------------------
# MET5 FILL
#----------------------------------------------------------------
templayer slots_m5
bbox top
slots 32000 11500 2500 32000 4500 2500
templayer obstruct_m5 allm5,allpad,allngf
grow 500
shrink 500
grow 500
layer met4fill slots_m5
and-not obstruct_m5
shrink 220
grow 220
end
#-----------------------------------------------------------------------
cifinput
#-----------------------------------------------------------------------
# NOTE: All values in this section MUST be multiples of 25
# or else magic will scale below the allowed layout grid size
#-----------------------------------------------------------------------
style vendorimport
scalefactor 10 nanometers
gridlimit 5
options ignore-unknown-layer-labels no-reconnect-labels
ignore NPC
ignore AREAID
layer nwell NWELL,WELLTXT,WELLPIN
labels NWELL
labels WELLTXT text
labels WELLPIN port
layer pwell PWELLTXT,PWELLPIN,SUBTXT
labels PWELLTXT text
labels PWELLPIN port
labels SUBTXT text
layer dnwell DNWELL
labels DNWELL
layer rpw PWRES
and DNWELL
labels PWRES
templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
and-not POLY
and-not NWELL
and-not PPLUS
and-not DIODE
and-not THKOX
and NPLUS
copyup ndifcheck
labels DIFF
labels DIFFTXT text
labels DIFFPIN port
labels TAPPIN port
layer ndiff ndiffarea
# Copy ndiff areas up for contact checks
templayer xndifcheck ndifcheck
copyup ndifcheck
templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
and-not POLY
and-not NWELL
and-not PPLUS
and-not DIODE
and THKOX
and NPLUS
copyup ndifcheck
labels DIFF
labels DIFFTXT text
labels DIFFPIN port
layer mvndiff mvndiffarea
# Copy ndiff areas up for contact checks
templayer mvxndifcheck mvndifcheck
copyup mvndifcheck
layer ndiode DIFF
and NPLUS
and DIODE
and-not NWELL
and-not POLY
and-not PPLUS
and-not THKOX
and-not LVTN
labels DIFF
layer ndiodelvt DIFF
and NPLUS
and DIODE
and-not NWELL
and-not POLY
and-not PPLUS
and-not THKOX
and LVTN
labels DIFF
templayer ndiodearea DIODE
and NPLUS
and-not THKOX
and-not NWELL
copyup DIODE,NPLUS
layer ndiffres DIFFRES
and NPLUS
and-not THKOX
labels DIFF
templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
and-not POLY
and NWELL
and-not NPLUS
and-not DIODE
and-not THKOX
and PPLUS
copyup pdifcheck
labels DIFF
labels DIFFTXT text
labels DIFFPIN port
layer pdiff pdiffarea
layer mvndiode DIFF
and NPLUS
and DIODE
and THKOX
and-not POLY
and-not PPLUS
and-not LVTN
labels DIFF
layer nndiode DIFF
and NPLUS
and DIODE
and THKOX
and-not POLY
and-not PPLUS
and LVTN
labels DIFF
templayer mvndiodearea DIODE
and NPLUS
and THKOX
and-not NWELL
copyup DIODE,NPLUS
layer mvndiffres DIFFRES
and NPLUS
and THKOX
labels DIFF
templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
and-not POLY
and NWELL
and-not NPLUS
and THKOX
and-not DIODE
and PPLUS
copyup mvpdifcheck
labels DIFF
labels DIFFTXT text
labels DIFFPIN port
layer mvpdiff mvpdiffarea
# Copy pdiff areas up for contact checks
templayer xpdifcheck pdifcheck
copyup pdifcheck
layer pdiode DIFF
and PPLUS
and-not POLY
and-not NPLUS
and-not THKOX
and-not LVTN
and-not HVTP
and DIODE
labels DIFF
layer pdiodelvt DIFF
and PPLUS
and-not POLY
and-not NPLUS
and-not THKOX
and LVTN
and-not HVTP
and DIODE
labels DIFF
layer pdiodehvt DIFF
and PPLUS
and-not POLY
and-not NPLUS
and-not THKOX
and-not LVTN
and HVTP
and DIODE
labels DIFF
templayer pdiodearea DIODE
and PPLUS
and-not THKOX
copyup DIODE,PPLUS
# Define pfet areas as known pdiff, regardless of the presence of a well.
templayer pfetarea DIFF
and-not NPLUS
and-not THKOX
and POLY
layer pfet pfetarea
and-not LVTN
and-not HVTP
labels DIFF
layer pfetlvt pfetarea
and LVTN
labels DIFF
layer pfethvt pfetarea
and HVTP
labels DIFF
# Always force nwell under pfet (nwell encloses pdiff by 0.18)
layer nwell pfetarea
grow 180
# Copy mvpdiff areas up for contact checks
templayer mvxpdifcheck mvpdifcheck
copyup mvpdifcheck
layer mvpdiode DIFF
and PPLUS
and-not POLY
and-not NPLUS
and THKOX
and DIODE
labels DIFF
templayer mvpdiodearea DIODE
and PPLUS
and THKOX
copyup DIODE,PPLUS
# Define pfet areas as known pdiff,
# regardless of the presence of a
# well.
templayer mvpfetarea DIFF
and-not NPLUS
and THKOX
and POLY
layer mvpfet mvpfetarea
labels DIFF
layer pdiff DIFF,DIFFTXT,DIFFPIN
and-not NPLUS
and-not POLY
and-not THKOX
labels DIFF
labels DIFFTXT text
labels DIFFPIN port
layer pdiffres DIFFRES
and PPLUS
and NWELL
and-not THKOX
labels DIFF
layer nfet DIFF
and POLY
and-not PPLUS
and NPLUS
and-not THKOX
and-not LVTN
and-not SONOS
labels DIFF
layer nfetlvt DIFF
and POLY
and-not PPLUS
and NPLUS
and-not THKOX
and LVTN
and-not SONOS
labels DIFF
layer nsonos DIFF
and POLY
and-not PPLUS
and NPLUS
and-not THKOX
and LVTN
and SONOS
labels DIFF
templayer nsdarea DIFF
and NPLUS
and NWELL
and-not POLY
and-not PPLUS
and-not THKOX
copyup nsubcheck
layer nsd nsdarea
labels DIFF
layer nsd TAP,TAPPIN
and NPLUS
labels TAP
labels TAPPIN port
templayer nsdexpand nsdarea
grow 500
# Copy nsub areas up for contact checks
templayer xnsubcheck nsubcheck
copyup nsubcheck
templayer psdarea DIFF
and PPLUS
and-not NWELL
and-not POLY
and-not NPLUS
and-not THKOX
and-not pfetexpand
copyup psubcheck
layer psd psdarea
labels DIFF
layer psd TAP,TAPPIN
and PPLUS
and-not THKOX
labels TAP
labels TAPPIN port
templayer psdexpand psdarea
grow 500
layer mvpdiff DIFF,DIFFTXT,DIFFPIN
and-not NPLUS
and-not POLY
and THKOX
and mvpfetexpand
labels DIFF
labels DIFFTXT text
labels DIFFPIN port
layer mvpdiffres DIFFRES
and PPLUS
and NWELL
and THKOX
and-not mvrdpioedge
labels DIFF
layer mvnfet DIFF
and POLY
and-not PPLUS
and NPLUS
and-not LVTN
and THKOX
labels DIFF
layer mvnnfet DIFF
and POLY
and-not PPLUS
and NPLUS
and LVTN
and THKOX
labels DIFF
templayer mvnsdarea DIFF
and NPLUS
and NWELL
and-not POLY
and-not PPLUS
and THKOX
copyup mvnsubcheck
layer mvnsd mvnsdarea
labels DIFF
layer mvnsd TAP,TAPPIN
and NPLUS
and THKOX
labels TAP
labels TAPPIN port
templayer mvnsdexpand mvnsdarea
grow 500
# Copy nsub areas up for contact checks
templayer mvxnsubcheck mvnsubcheck
copyup mvnsubcheck
templayer mvpsdarea DIFF
and PPLUS
and-not NWELL
and-not POLY
and-not NPLUS
and THKOX
and-not mvpfetexpand
copyup mvpsubcheck
layer mvpsd mvpsdarea
labels DIFF
layer mvpsd TAP,TAPPIN
and PPLUS
and THKOX
labels TAP
labels TAPPIN port
templayer mvpsdexpand mvpsdarea
grow 500
# Copy psub areas up for contact checks
templayer xpsubcheck psubcheck
copyup psubcheck
templayer mvxpsubcheck mvpsubcheck
copyup mvpsubcheck
layer psd DIFF
and-not PPLUS
and-not NPLUS
and-not POLY
and-not THKOX
and-not pfetexpand
and psdexpand
layer nsd DIFF
and-not PPLUS
and-not NPLUS
and-not POLY
and-not THKOX
and nsdexpand
layer mvpsd DIFF
and-not PPLUS
and-not NPLUS
and-not POLY
and THKOX
and-not mvpfetexpand
and mvpsdexpand
layer mvnsd DIFF
and-not PPLUS
and-not NPLUS
and-not POLY
and THKOX
and mvnsdexpand
templayer hresarea POLY
and RPM
grow 3000
templayer diffresarea DIFFRES
and-not THKOX
grow 3000
templayer mvdiffresarea DIFFRES
and THKOX
grow 3000
templayer resarea diffresarea,mvdiffresarea,hresarea,xresarea
layer pfet POLY
and DIFF
and diffresarea
and-not NPLUS
templayer polyarea POLY
and-not POLYRES
and-not DIFF
copyup polycheck
layer poly polyarea,POLYTXT,POLYPIN
labels POLY
labels POLYTXT text
labels POLYPIN port
# Copy (non-resistor) poly areas up for contact checks
templayer xpolycheck polycheck
copyup polycheck
layer mrp1 POLY
and POLYRES
and-not RPM
labels POLY
layer xhrpoly POLY
and POLYRES
and RPM
and PPLUS
and NPC
labels POLY
layer ndc CONT
and DIFF
and NPLUS
and-not NWELL
and LI
and-not THKOX
layer nsc CONT
and DIFF,TAP
and NPLUS
and NWELL
and LI
and-not THKOX
layer pdc CONT
and DIFF
and PPLUS
and NWELL
and LI
and-not THKOX
layer pdc CONT
and DIFF
and PPLUS
and pfetexpand
and LI
and-not THKOX
layer psc CONT
and DIFF,TAP
and PPLUS
and-not NWELL
and-not pfetexpand
and LI
and-not THKOX
layer pc CONT
and POLY
and-not DIFF
and LI
layer ndic CONT
and DIFF
and NPLUS
and DIODE
and-not POLY
and-not PPLUS
and-not THKOX
and-not LVTN
layer ndilvtc CONT
and DIFF
and NPLUS
and DIODE
and-not POLY
and-not PPLUS
and-not THKOX
and LVTN
layer pdic CONT
and DIFF
and PPLUS
and DIODE
and-not POLY
and-not NPLUS
and-not THKOX
and-not LVTN
and-not HVTP
layer pdilvtc CONT
and DIFF
and PPLUS
and DIODE
and-not POLY
and-not NPLUS
and-not THKOX
and LVTN
and-not HVTP
layer pdihvtc CONT
and DIFF
and PPLUS
and DIODE
and-not POLY
and-not NPLUS
and-not THKOX
and-not LVTN
and HVTP
layer mvndc CONT
and DIFF
and NPLUS
and-not NWELL
and LI
and THKOX
layer mvnsc CONT
and DIFF,TAP
and NPLUS
and NWELL
and LI
and THKOX
layer mvpdc CONT
and DIFF
and PPLUS
and NWELL
and LI
and THKOX
layer mvpdc CONT
and DIFF
and PPLUS
and mvpfetexpand
and MET1
and THKOX
layer mvpsc CONT
and DIFF,TAP
and PPLUS
and-not NWELL
and-not mvpfetexpand
and LI
and THKOX
layer mvndic CONT
and DIFF
and NPLUS
and DIODE
and-not POLY
and-not PPLUS
and THKOX
layer mvpdic CONT
and DIFF
and PPLUS
and DIODE
and-not POLY
and-not NPLUS
and THKOX
layer locali LI,LITXT,LIPIN
labels LI
labels LITXT text
labels LIPIN port
layer lic MCON
labels MCON
layer m1 MET1
and resarea
layer m1 MET1,MET1TXT,MET1PIN
labels MET1
labels MET1TXT text
labels MET1PIN port
layer mimcap MET3
and CAPM
labels CAPM
layer mimcc VIA2
and CAPM
grow 150
labels CAPM
layer mimcap2 MET4
and CAPM2
labels CAPM2
layer mim2cc VIA3
and CAPM2
grow 150
labels CAPM2
layer m2c VIA1
grow 55
grow 30
shrink 30
layer m2 MET2,MET2TXT,MET2PIN
labels MET2
labels MET2TXT text
labels MET2PIN port
layer m3c VIA2
grow 40
grow 60
shrink 60
layer m3 MET3,MET3TXT,MET3PIN
labels MET3
labels MET3TXT text
labels MET3PIN port
layer via3 VIA3
grow 60
grow 40
shrink 40
layer m4 MET4,MET4TXT,MET4PIN
labels MET4
labels MET4TXT text
labels MET4PIN port
layer m5 MET5,MET5TXT,MET5PIN
labels MET5
labels MET5TXT text
labels MET5PIN port
layer via4 VIA4
grow 190
grow 210
shrink 210
layer metrdl RDL,RDLTXT,RDLPIN
labels RDL
labels RDLTXT text
labels RDLPIN port
# Find diffusion not covered in
# NPLUS or PPLUS and pull it into
# the next layer up
templayer gentrans DIFF
and-not PPLUS
and-not NPLUS
and POLY
copyup DIFF,POLY
templayer gendiff DIFF,TAP
and-not PPLUS
and-not NPLUS
and-not POLY
copyup DIFF
# Handle contacts found by copyup
layer ndic CONT
and MET1
and DIODE
and NPLUS
and-not THKOX
layer mvndic CONT
and MET1
and DIODE
and NPLUS
and THKOX
layer pdic CONT
and MET1
and DIODE
and PPLUS
and-not THKOX
layer mvpdic CONT
and MET1
and DIODE
and PPLUS
and THKOX
layer ndc CONT
and ndifcheck
layer mvndc CONT
and mvndifcheck
layer pdc CONT
and pdifcheck
layer mvpdc CONT
and mvpdifcheck
layer pc CONT
and polycheck
layer nsc CONT
and nsubcheck
layer mvnsc CONT
and mvnsubcheck
layer psc CONT
and psubcheck
layer mvpsc CONT
and mvpsubcheck
# Find contacts not covered in
# metal and pull them into the
# next layer up
templayer gencont CONT
and LI
and-not DIFF,TAP
and-not POLY
and-not DIODE
and-not nsubcheck
and-not psubcheck
and-not mvnsubcheck
and-not mvpsubcheck
copyup CONT,MET1
templayer barecont CONT
and-not LI
and-not nsubcheck
and-not psubcheck
and-not mvnsubcheck
and-not mvpsubcheck
copyup CONT
layer glass GLASS,PADTXT,PADPIN
labels GLASS
labels PADTXT text
labels PADPIN port
templayer boundary BOUND
boundary
layer comment LVSTEXT
labels LVSTEXT text
layer comment TTEXT
labels TTEXT text
layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
# MOS Varactor
layer var POLY
and DIFF
and NPLUS
and NWELL
and-not THKOX
grow 25
labels POLY
layer mvvar POLY
and DIFF
and NPLUS
and NWELL
and THKOX
grow 25
labels POLY
calma NWELL 64 20
calma DIFF 65 20
calma DNWELL 64 18
calma PWRES 64 13
calma TAP 65 44
# LVTN
calma LVTN 125 44
# HVTP
calma HVTP 78 44
# SONOS (TUNM)
calma SONOS 80 20
# NPLUS = NSDM
calma NPLUS 93 44
# PPLUS = PSDM
calma PPLUS 94 20
# HVI
calma THKOX 75 20
# NPC
calma NPC 95 20
# P+ POLY MASK
calma RPM 86 20
# Poly resistor ID mark
calma POLYRES 66 13
# Diffusion resistor ID mark
calma DIFFRES 65 13
calma POLY 66 20
# Diode ID mark
calma DIODE 81 23
# LICON
calma CONT 66 44
calma LI 67 20
calma MCON 67 44
calma MET1 68 20
calma VIA1 68 44
calma MET2 69 20
calma VIA2 69 44
calma MET3 70 20
calma VIA3 70 44
calma MET4 71 20
calma VIA4 71 44
calma MET5 72 20
calma RDL 74 20
calma GLASS 76 20
calma PADPIN 76 5
calma DIFFPIN 65 6
calma TAPPIN 65 5
calma WELLPIN 64 5
calma PWELLPIN 122 16
calma LIPIN 67 5
calma POLYPIN 66 5
calma MET1PIN 68 5
calma MET2PIN 69 5
calma MET3PIN 70 5
calma MET4PIN 71 5
calma MET5PIN 72 5
calma RDLPIN 74 5
calma SUBTXT 64 59
calma PADTXT 76 16
calma DIFFTXT 65 16
calma POLYTXT 66 16
calma WELLTXT 64 16
calma PWELLTXT 122 16
calma LITXT 67 16
calma MET1TXT 68 16
calma MET2TXT 69 16
calma MET3TXT 70 16
calma MET4TXT 71 16
calma MET5TXT 72 16
calma RDLPIN 74 16
calma BOUND 81 4
calma LVSTEXT 83 44
calma CAPM 89 44
calma CAPM 97 44
calma FILLOBSM1 62 24
calma FILLOBSM2 105 52
calma FILLOBSM3 107 24
calma FILLOBSM4 112 4
end
#-----------------------------------------------------
# Digital flow maze router cost parameters
#-----------------------------------------------------
mzrouter
end
#-----------------------------------------------------
# Vendor DRC rules
#-----------------------------------------------------
drc
style drc variants (fast),(full),(routing)
scalefactor 10
cifstyle drc
variants (fast),(full)
#-----------------------------
# DNWELL
#-----------------------------
width dnwell 3000 "Deep N-well width < %d (Dnwell 2)"
spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (Dnwell 3)"
spacing dnwell allnwell 4500 surround_ok \
"Deep N-well spacing to N-well < %d (Nwell 7)"
cifmaxwidth nwell_missing 1 bend_illegal \
"N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (Nwell 5a, 7)"
cifmaxwidth dnwell_missing 1 bend_illegal \
"SONOS nFET must be in Deep N-well (Tunm 6a)"
#-----------------------------
# NWELL
#-----------------------------
width allnwell 840 "N-well width < %d (Nwell 1)"
spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (Nwell 2a)"
#-----------------------------
# DIFF
#-----------------------------
width *ndiff,nfet,*nsd,*ndiode,ndiffres,*pdiff,pfet,*psd,*pdiode,pdiffres 150 \
"Diffusion width < %d (Diff/tap 1)"
width *mvndiff,mvnfet,mvnnfet,*mvnsd,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,*mvpsd,*mvpdiode,mvpdiffres 150 \
"Diffusion width < %d (Diff/tap 1)"
spacing alldifflv,var,alldiffmv,mvvar alldifflv,var,alldiffmv,mvvar 270 touching_ok \
"Diffusion spacing < %d (Diff/tap 3)"
spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
"N-Diffusion spacing to N-well < %d (Diff/tap 9)"
spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \
"N-Diffusion spacing to N-well < %d (Diff/tap 9)"
spacing *psd allnwell 130 touching_illegal \
"P-tap spacing to N-well < %d (Diff/tap 11)"
spacing *mvpsd allnwell 130 touching_illegal \
"P-tap spacing to N-well < %d (Diff/tap 11)"
surround *nsd allnwell 180 absence_illegal "N-well overlap of N-tap < %d (Diff/tap 10)"
surround *mvnsd,*nndiode allnwell 180 absence_illegal "N-well overlap of N-tap < %d (Diff/tap 10)"
surround *pdiff,*pdiode,pfet allnwell 180 absence_illegal \
"N-well overlap of P-Diffusion < %d (Diff/tap 8)"
surround *mvpdiff,*mvpdiode,mvpfet allnwell 180 absence_illegal \
"N-well overlap of P-Diffusion < %d (Diff/tap 8)"
variants (full)
cifmaxwidth ptap_missing 6000 bend_illegal \
"N-diff distance to P-tap must be < %d (tap rule)"
cifmaxwidth ntap_missing 6000 bend_illegal \
"P-diff distance to N-tap must be < %d (tap rule)"
cifmaxwidth mvntap_missing 6000 bend_illegal \
"5.0V P-diff distance to 5.0V N-tap must be < %d (tap rule)"
cifmaxwidth mvptap_missing 6000 bend_illegal \
"5.0V P-diff distance to 5.0V N-tap must be < %d (tap rule)"
variants *
#-----------------------------
# POLY
#-----------------------------
width allpoly 150 "Poly width < %d (Poly 1a)"
spacing allpoly allpoly 210 touching_ok "Poly spacing < %d (Poly 2)"
spacing allpolynonfet alldifflvnonfet 75 corner_ok allfets \
"Poly spacing to Diffusion < %d (Poly 4a)"
overhang *ndiff,rndiff nfet 250 "N-Diffusion overhang of nmos < %d (Poly 7)"
overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 "N-Diffusion overhang of nmos < %d (Poly 7)"
overhang *pdiff,rpdiff pfet 250 "P-Diffusion overhang of pmos < %d (Poly 7)"
overhang *mvpdiff,mvrpdiff mvpfet 250 "P-Diffusion overhang of pmos < %d (Poly 7)"
overhang *poly allfets 130 "Poly overhang of transistor < %d (Poly 8)"
#--------------------------------------------------------------------
# NPC (Nitride Poly Cut)
#--------------------------------------------------------------------
# Layer NPC is defined automatically around poly contacts (grow 0.1um)
#--------------------------------------------------------------------
# CONT (LICON, contact between poly/diff and LI)
#--------------------------------------------------------------------
width ndc/li 170 "N-diffusion contact width < %d (LIcon 1)"
width nsc/li 170 "N-tap contact width < %d (LIcon 1)"
width pdc/li 170 "P-diffusion contact width < %d (LIcon 1)"
width psc/li 170 "P-tap contact width < %d (LIcon 1)"
width ndic/li 170 "N-diode contact width < %d (LIcon 1)"
width pdic/li 170 "P-diode contact width < %d (LIcon 1)"
width pc/li 170 "Poly contact width < %d (LIcon 1)"
width mvndc/li 170 "N-diffusion contact width < %d (LIcon 1)"
width mvnsc/li 170 "N-tap contact width < %d (LIcon 1)"
width mvpdc/li 170 "P-diffusion contact width < %d (LIcon 1)"
width mvpsc/li 170 "P-tap contact width < %d (LIcon 1)"
width mvndic/li 170 "N-diode contact width < %d (LIcon 1)"
width mvpdic/li 170 "P-diode contact width < %d (LIcon 1)"
spacing allpdiffcont allndiffcont 170 touching_illegal "Diffusion contact spacing < %d (LIcon 2)"
spacing allndiffcont allndiffcont 170 touching_ok "Diffusion contact spacing < %d (LIcon 2)"
spacing allpdiffcont allpdiffcont 170 touching_ok "Diffusion contact spacing < %d (LIcon 2)"
spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (LIcon 2)"
spacing pc alldiff 190 touching_illegal "Poly contact spacing to diffusion < %d (LIcon 14)"
spacing ndc,pdc nfet,pfet 55 touching_illegal \
"Diffusion contact to gate < %d (LIcon 11)"
spacing mvndc,mvpdc mvnfet,mvnnfet,mvpfet 55 touching_illegal \
"Diffusion contact to gate < %d (LIcon 11)"
spacing ndc,mvndc rnd,mvrnd 60 touching_illegal "Diffusion contact to rndiff < %d ()"
spacing pdc,mvpdc rdp,mvrdp 60 touching_illegal "Diffusion contact to rndiff < %d ()"
surround ndc/a *ndiff 40 absence_illegal \
"N-diffusion overlap of N-diffusion contact < %d (LIcon 5a)"
surround pdc/a *pdiff 40 absence_illegal \
"P-diffusion overlap of P-diffusion contact < %d (LIcon 5a)"
surround ndic/a *ndi 40 absence_illegal \
"N-diode overlap of N-diode contact < %d (LIcon 5a)"
surround pdic/a *pdi 40 absence_illegal \
"P-diode overlap of N-diode contact < %d (LIcon 5a)"
surround ndc/a *ndiff,nfet 60 directional \
"N-diffusion overlap of N-diffusion contact < %d in one direction (LIcon 5c)"
surround pdc/a *pdiff,pfet 60 directional \
"P-diffusion overlap of P-diffusion contact < %d in one direction (LIcon 5c)"
surround ndic/a *ndi 60 directional \
"N-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
surround pdic/a *pdi 60 directional \
"P-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
surround nsc/a *nsd 120 directional \
"N-tap overlap of N-tap contact < %d in one direction (LIcon 7)"
surround psc/a *psd 120 directional \
"P-tap overlap of P-tap contact < %d in one direction (LIcon 7)"
surround mvndc/a *mvndiff 40 absence_illegal \
"N-diffusion overlap of N-diffusion contact < %d (LIcon 5a)"
surround mvpdc/a *mvpdiff 40 absence_illegal \
"P-diffusion overlap of P-diffusion contact < %d (LIcon 5a)"
surround mvndic/a *mvndi 40 absence_illegal \
"N-diode overlap of N-diode contact < %d (LIcon 5a)"
surround mvpdic/a *mvpdi 40 absence_illegal \
"P-diode overlap of N-diode contact < %d (LIcon 5a)"
surround mvndc/a *mvndiff,mvnfet 60 directional \
"N-diffusion overlap of N-diffusion contact < %d in one direction (LIcon 5c)"
surround mvpdc/a *mvpdiff,mvpfet 60 directional \
"P-diffusion overlap of P-diffusion contact < %d in one direction (LIcon 5c)"
surround mvndic/a *mvndi 60 directional \
"N-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
surround mvpdic/a *mvpdi 60 directional \
"P-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
surround mvnsc/a *mvnsd 120 directional \
"N-tap overlap of N-tap contact < %d in one direction (LIcon 7)"
surround mvpsc/a *mvpsd 120 directional \
"P-tap overlap of P-tap contact < %d in one direction (LIcon 7)"
surround pc/a *poly,mrp1,xhrpoly 80 absence_illegal \
"Poly overlap of poly contact < %d (LIcon 8, 8a)"
exact_overlap ndc/a,pdc/a,psc/a,nsc/a,pc/a,ndic/a,pdic/a
exact_overlap mvndc/a,mvpdc/a,mvpsc/a,mvnsc/a,mvndic/a,mvpdic/a
#-------------------------------------------------------------
# LI - Local interconnect layer
#-------------------------------------------------------------
width *li,rli 170 "Local interconnect width < %d (LI 1)"
spacing allli allli,obsli 170 touching_ok "Local interconnect spacing < %d (LI 3)"
surround pc/li *li 80 directional \
"Local interconnect overlap of poly contact < %d in one direction (LI 5)"
surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
*li 80 directional \
"Local interconnect overlap of diffusion contact < %d in one direction (LI 5)"
area allli,obsli 56100 170 "Local interconnect minimum area < %a (LI 6)"
#-------------------------------------------------------------
# MCON - Contact between local interconnect and metal1
#-------------------------------------------------------------
width lic/m1 170 "Mcon width < %d (Mcon 1)"
spacing lic/m1 lic/m1 170 touching_ok "Mcon spacing < %d (Mcon 2)"
exact_overlap lic/m1
#-------------------------------------------------------------
# METAL1 -
#-------------------------------------------------------------
width *m1,rm1 140 "Metal1 width < %d (Met1 1)"
spacing allm1 allm1,obsm1 140 touching_ok "Metal1 spacing < %d (Met1 2)"
area allm1,obsm1 83000 140 "Metal1 minimum area < %a (Met1 6)"
surround lic/m1 *met1 30 absence_illegal \
"Metal1 overlap of local interconnect contact < %d (Met1 4)"
surround lic/m1 *met1 60 directional \
"Metal1 overlap of local interconnect contact < %d in one direction (Met1 5)"
variants (fast),(full)
widespacing allm1 3000 allm1,obsm1 280 touching_ok \
"Metal1 > 3um spacing to unrelated m1 < %d (Met1 3a)"
variants *
#--------------------------------------------------
# VIA1
#--------------------------------------------------
width v1/m1 260 "Via1 width < %d (Via 1a + 2 * Via 4a)"
spacing v1 v1 60 touching_ok "Via1 spacing < %d (Via 2 - 2 * Via 4a)"
surround v1/m1 *m1 30 directional \
"Metal1 overlap of Via1 < %d in one direction (Via 5a - Via 4a)"
surround v1/m2 *m2 30 directional \
"Metal2 overlap of Via1 < %d in one direction (Met2 5 - Met2 4)"
exact_overlap v1/m2
#--------------------------------------------------
# METAL2 -
#--------------------------------------------------
width allm2 140 "Metal2 width < %d (Met2 1)"
spacing allm2 allm2,obsm2 140 touching_ok "Metal2 spacing < %d (Met2 2)"
area allm2,obsm2 67600 140 "Metal2 minimum area < %a (Met2 6)"
variants (fast),(full)
widespacing allm2 3000 allm2,obsm2 280 touching_ok \
"Metal2 > 3um spacing to unrelated m2 < %d (Met2 3)"
variants *
#--------------------------------------------------
# VIA2
#--------------------------------------------------
width v2/m2 280 "Via2 width < %d (Via2 1a + 2 * Via2 4)"
spacing v2 v2 120 touching_ok "Via2 spacing < 0.24um (Via2 2 - 2 * Via2 4)"
surround v2/m2 *m2 45 directional \
"Metal2 overlap of Via2 < %d in one direction (Via2 4a - Via2 4)"
surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of Via2 < %d (Met3 4)"
exact_overlap v2/m2
#--------------------------------------------------
# METAL3 -
#--------------------------------------------------
width allm3 300 "Metal3 width < %d (Met3 1)"
spacing allm3 allm3,obsm3 300 touching_ok "Metal3 spacing < %d (Met3 2)"
area allm3,obsm3 240000 300 "Metal3 minimum area < %a (Met3 6)"
variants (fast),(full)
widespacing allm3 3000 allm3,obsm3 400 touching_ok \
"Metal3 > 3um spacing to unrelated m3 < %d (Met3 3d)"
variants *
#--------------------------------------------------
# VIA3 - Requires 1 Module
#--------------------------------------------------
width v3/m3 320 "Via3 width < %d (Via3 1 + 2 * Via3 4)"
spacing v3 v3 80 touching_ok "Via3 spacing < %d (Via3 2 - 2 * Via3 4)"
surround v3/m3 *m3 30 directional \
"Metal3 overlap of Via3 in one direction < %d (Via3 5 - Via3 4)"
surround v3/m4 *m4 5 directional \
"Metal4 overlap of Via3 in one direction < %d (Met4 3 - Via3 4)"
exact_overlap v3/m3
#-----------------------------
# METAL4 - METAL4 Module
#-----------------------------
variants *
width allm4 300 "Metal4 width < %d (Met4 1)"
spacing allm4 allm4,obsm4 300 touching_ok "Metal4 spacing < %d (Met4 2)"
area allm4,obsm4 240000 300 "Metal4 minimum area < %a (Met4 4a)"
variants (fast),(full)
widespacing allm4 3000 allm4,obsm4 400 touching_ok \
"Metal4 > 3um spacing to unrelated m4 < %d (S2M4)"
variants *
#--------------------------------------------------
# VIA4 - Requires 1 Module
#--------------------------------------------------
width v4/m4 1180 "Via4 width < %d (Via4 1 + 2 * Via4 4)"
spacing v4 v4 420 touching_ok "Via4 spacing < %d (Via4 2 - 2 * Via4 4)"
surround v4/m5 *m5 120 absence_illegal \
"Metal5 overlap of Via4 < %d (Met5 3 - Via4 4)"
exact_overlap v4/m4
#-----------------------------
# 1 - 1 Module
#-----------------------------
width allm5 1600 "Metal5 width < %d (Met5 1)"
spacing allm5 allm5,obsm5 1600 touching_ok "Metal5 spacing < %d (Met5 2)"
area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (Met5 4)"
variants (full)
width metrdl 10000 "RDL width < %d (Rdl 1)"
spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (Rdl 2)"
surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (Rdl 3)"
spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (Rdl 6)"
variants *
#--------------------------------------------------
# NMOS, PMOS
#--------------------------------------------------
extend allfets *poly 420 "Transistor width < %d (Diff/tap 2)"
# Except: Note that standard cells allow transistor width minimum 0.36um
spacing *nsd,*mvnsd pfet,mvpfet 300 touching_illegal \
"N-tap spacing to PMOS gate < %d (Poly 6)"
spacing *psd,*mvpsd nfet,mvnfet 300 touching_illegal \
"P-tap spacing to NMOS gate < %d (Poly 6)"
#--------------------------------------------------
# mrp1 (N+ poly resistor)
#--------------------------------------------------
width mrp1 330 "mrp1 resistor width < %d (Poly 3)"
# spacing mrp1 pc 120 touching_illegal "mrp1 spacing to Cont < 0.12um ()"
#--------------------------------------------------
# xhrpoly (P+ poly resistor)
#--------------------------------------------------
width xhrpoly 350 "xhrpoly resistor width < %d (P+ Poly 1a)"
# NOTE: xhrpoly resistor requires choice of discrete widths 0.35, 0.69, ... up to 1.27.
# spacing xhrpoly pc 120 touching_illegal "xhrpoly spacing to Cont < 0.12um ()"
#------------------------------------
# MOS Varactor device rules
#------------------------------------
#
overhang nsd var 250 \
"N-Tap overhang of Varactor < %d (Var 4)"
overhang mvnsd mvvar 250 \
"N-Tap overhang of Varactor < %d (Var 4)"
width var,mvvar 180 "Varactor length < %d (Var 1)"
extend var,mvvar *poly 1000 "Transistor width < %d (Var 2)"
#-----------------------------------------------------------
# 1CAP - (work in progress)
#-----------------------------------------------------------
width *mimcap 2000 "MiM cap width < 5.00um ()"
maxwidth *mimcap 30000 bend_ok "MiM cap width > 30.0um ()"
spacing *mimcap *mimcap 1500 touching_ok "MiM cap spacing < 1.50um ()"
spacing *mimcap via2/m3 850 touching_illegal \
"MiM cap spacing to via2 < 0.85um ()"
width mimcapc/m2 660 "MiM Contact width < 0.66um ()"
surround *mimcc *mimcap 150 absence_illegal \
"MiM cap must surround MiM cap contact by 0.15um ()"
spacing pad *mimcap 50 touching_illegal "MiM cap cannot overlap pad ()"
surround *mimcap *metal2/m2 500 absence_illegal \
"Metal3 must surround MiM cap by 0.5um ()"
spacing via2 *mimcap 50 touching_illegal "MiM cap cannot overlap via2 ()"
surround *mimcap *metal3/m3 500 absence_illegal \
"Metal4 must surround MiM cap by 0.5um ()"
spacing via3 *mimcap 50 touching_illegal "MiM cap cannot overlap via3 ()"
width *mimcap2 2000 "MiM cap width < 5.00um ()"
maxwidth *mimcap2 30000 bend_ok "MiM cap width > 30.0um ()"
spacing *mimcap2 *mimcap2 1500 touching_ok "MiM cap spacing < 1.50um ()"
spacing *mimcap2 via3/m4 850 touching_illegal \
"MiM cap spacing to via3 < 0.85um ()"
width mimcap2c/m3 660 "MiM Contact width < 0.66um ()"
surround *mim2cc *mimcap2 150 absence_illegal \
"MiM cap must surround MiM cap contact by 0.15um ()"
spacing pad *mimcap2 50 touching_illegal "MiM cap cannot overlap pad ()"
surround *mimcap2 *metal3/m3 500 absence_illegal \
"Metal3 must surround MiM cap by 0.5um ()"
spacing via3 *mimcap2 50 touching_illegal "MiM cap cannot overlap via3 ()"
surround *mimcap2 *metal4/m4 500 absence_illegal \
"Metal4 must surround MiM cap by 0.5um ()"
spacing via4 *mimcap2 50 touching_illegal "MiM cap cannot overlap via4 ()"
#----------------------------
# End DRC style
#----------------------------
end
#----------------------------
# LEF format definitions
#----------------------------
lef
routing li LI1 li1 LI li
routing m1 MET1 m1 met1
routing m2 MET2 m2 met2
routing m3 MET3 m3 met3
routing m4 MET4 m4 met4
routing m5 MET5 m5 met5
cut lic MCON Mcon mcon
cut m2c VIA1 via1 cont2 via12
cut m3c VIA2 via2 cont3 via23
cut via3 VIA3 via3 cont4 via34
cut via4 VIA4 via4 cont5 via45
obs obsli LI1
obs obsm1 MET1
obs obsm2 MET2
obs obsm3 MET3
obs obsm4 MET4
obs obsm5 MET5
# Map contact obstructions to the base metal layer
obs obsli MCON
obs obsm1 VIA1
end
#-----------------------------------------------------
# Device and Parasitic extraction
#-----------------------------------------------------
extract
style ngspice variants (sim),(lvs)
cscale 1
lambda 1.0
units microns
step 100
sidehalo 8
planeorder dwell 0
planeorder well 1
planeorder active 2
planeorder locali 3
planeorder metal1 4
planeorder metal2 5
planeorder metal3 6
planeorder metal4 7
planeorder metal5 8
planeorder metali 9
planeorder block 10
planeorder comment 11
substrate *ppdiff,*mvppdiff,space/w,pwell well -dnwell
# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
# Resistances are in milliohms per square
# Optional 3rd argument is the corner adjustment fraction
resist (nwell)/well 975000
resist (rpw)/well 975000 0.5
resist (pwell)/well 975000
resist (*ndiff,nsd)/active 7500
resist (*pdiff,*psd)/active 7100
resist (*mvndiff,mvnsd)/active 7500
resist (*mvpdiff,*mvpsd)/active 7100
resist ndiffres/active 120000 0.5
resist pdiffres/active 197000 0.5
resist mvndiffres/active 120000 0.5
resist mvpdiffres/active 197000 0.5
resist mrp1/active 48200 0.5
# NOTE: Have not found P+ poly resistance in documentation
resist xhrpoly/active 55000 0.5
resist (allpolynonres)/active 48200
resist (allli)/locali 12800
resist (allm1)/metal1 125
resist (allm2)/metal2 125
resist (allm3)/metal3 47
resist (allm4)/metal4 47
resist (allm5)/metal5 29
contact ndc,nsc 15000
contact pdc,psc 15000
contact mvndc,mvnsc 15000
contact mvpdc,mvpsc 15000
contact pc 15000
contact lic 152000
contact m2c 4500
contact m3c 3410
contact mimcc 4500
contact mim2cc 3410
contact via3 3410
contact via4 380
#-------------------------------------------------------------------------
# Parasitic capacitance values: Use document (...)
#-------------------------------------------------------------------------
# This uses the new "default" definitions that determine the intervening
# planes from the planeorder stack, take care of the reflexive sideoverlap
# definitions, and generally clean up the section and make it more readable.
#
# Also uses "units microns" statement, so all parasitic capacitance values
# are taken directly from the source document PDS_035_03, in units of
# aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
#-------------------------------------------------------------------------
# Remember that device capacitances to substrate are taken care of by the
# models. Thus, active and poly definitions ignore all "fet" types.
# fet types are excluded when computing parasitic capacitance to
# active from layers above them because poly is a shield; fet types are
# included for parasitics from layers above to poly. Resistor types
# should be removed from all parasitic capacitance calculations, or else
# they just create floating caps. Technically, the capacitance probably
# should be split between the two terminals. Unsure of the correct model.
#-------------------------------------------------------------------------
variant (sim)
#n-well
# NOTE: This value not found in PEX files
defaultareacap nwell well 120
#n-active
# Rely on device models to capture *ndiff area cap
# Do not extract parasitics from resistors
# defaultareacap allnactivenonfet active 790
# defaultperimeter allnactivenonfet active 280
#p-active
# Rely on device models to capture *pdiff area cap
# Do not extract parasitics from resistors
# defaultareacap allpactivenonfet active 810
# defaultperimeter allpactivenonfet active 300
#poly
# Do not extract parasitics from resistors
# defaultsidewall allpolynonfet active 22
# defaultareacap allpolynonfet active 105
# defaultperimeter allpolynonfet active 57
defaultsidewall *poly active 63
defaultareacap *poly active nwell,obswell,pwell well 63
defaultperimeter *poly active nwell,obswell,pwell well 16
#locali
defaultsidewall allm1 metal1 113
defaultareacap allm1 metal1 nwell,obswell,pwell well 37
defaultperimeter allm1 metal1 nwell,obswell,pwell well 8
defaultoverlap allm1 metal1 nwell well 37
#locali->diff
defaultoverlap allm1 metal1 allactivenonfet active 36
defaultsideoverlap allm1 metal1 allactivenonfet active 9
#locali->poly
defaultoverlap allm1 metal1 allpolynonres active 46
defaultsideoverlap allm1 metal1 allpolynonres active 10
#metal1
defaultsidewall allm1 metal1 113
defaultareacap allm1 metal1 nwell,obswell,pwell well 17
defaultperimeter allm1 metal1 nwell,obswell,pwell well 8
defaultoverlap allm1 metal1 nwell well 26
#metal1->locali
defaultoverlap allm1 metal1 allactivenonfet active 36
defaultsideoverlap allm1 metal1 allactivenonfet active 9
#metal1->diff
defaultoverlap allm1 metal1 allactivenonfet active 36
defaultsideoverlap allm1 metal1 allactivenonfet active 9
#metal1->poly
defaultoverlap allm1 metal1 allpolynonres active 46
defaultsideoverlap allm1 metal1 allpolynonres active 10
#metal2
defaultsidewall allm2 metal2 101
defaultareacap allm2 metal2 nwell,obswell,pwell well 12
defaultperimeter allm2 metal2 nwell,obswell,pwell well 6
defaultoverlap allm2 metal2 nwell well 13
#metal2->diff
defaultoverlap allm2 metal2 allactivenonfet active 14
defaultsideoverlap allm2 metal2 allactivenonfet active 7
#metal2->poly
defaultoverlap allm2 metal2 allpolynonres active 16
defaultsideoverlap allm2 metal2 allpolynonres active 7
#metal2->metal1
defaultoverlap allm2 metal2 allm1 metal1 39
defaultsideoverlap allm2 metal2 allm1 metal1 10
#metal3
defaultsidewall allm3 metal3 102
defaultoverlap allm3 metal3 nwell well 8
defaultareacap allm3 metal3 nwell,obswell,pwell well 8
defaultperimeter allm3 metal3 nwell,obswell,pwell well 5
#metal3->diff
defaultoverlap allm3 metal3 allactive active 9
defaultsideoverlap allm3 metal3 allactive active 6
#metal3->poly
defaultoverlap allm3 metal3 allpolynonres active 10
defaultsideoverlap allm3 metal3 allpolynonres active 6
#metal3->metal1
defaultoverlap allm3 metal3 allm1 metal1 15
defaultsideoverlap allm3 metal3 allm1 metal1 7
#metal3->metal2
defaultoverlap allm3 metal3 allm2 metal2 39
defaultsideoverlap allm3 metal3 allm2 metal2 10
#metal4
defaultsidewall allm4 metal4 102
# defaultareacap alltopm metal4 well 6
areacap allm4/m4 8
defaultoverlap allm4 metal4 nwell well 8
defaultperimeter allm4 metal4 well 5
#metal4->diff
defaultoverlap allm4 metal4 allactivenonfet active 7
defaultsideoverlap allm4 metal4 allactivenonfet active 7
#metal4->poly
defaultoverlap allm4 metal4 allpolynonres active 7
defaultsideoverlap allm4 metal4 allpolynonres active 5
#metal4->metal1
defaultoverlap allm4 metal4 allm1 metal1 9
defaultsideoverlap allm4 metal4 allm1 metal1 6
#metal4->metal2
defaultoverlap allm4 metal4 allm2 metal2 15
defaultsideoverlap allm4 metal4 allm2 metal2 7
#metal4->metal3
defaultoverlap allm4 metal4 allm3 metal3 39
defaultsideoverlap allm4 metal4 allm3 metal3 10
#metal5
defaultsidewall allm5 metal5 103
# defaultareacap allm5 metal5 well 6
areacap allm5/m5 6
defaultoverlap allm5 metal5 nwell well 6
defaultperimeter allm5 metal5 well 5
#metal5->diff
defaultoverlap allm5 metal5 allactivenonfet active 5
defaultsideoverlap allm5 metal5 allactivenonfet active 5
#metal5->poly
defaultoverlap allm5 metal5 allpolynonres active 5
defaultsideoverlap allm5 metal5 allpolynonres active 5
#metal5->metal1
defaultoverlap allm5 metal5 allm1 metal1 7
defaultsideoverlap allm5 metal5 allm1 metal1 5
#metal5->metal2
defaultoverlap allm5 metal5 allm2 metal2 9
defaultsideoverlap allm5 metal5 allm2 metal2 6
#metal5->metal3
defaultoverlap allm5 metal5 allm3 metal3 15
defaultsideoverlap allm5 metal5 allm3 metal3 7
#metal5->metal4
defaultoverlap allm5 metal5 allm4 metal4 39
defaultsideoverlap allm5 metal5 allm4 metal4 10
# Devices: Use document (...)
device msubcircuit pshort pfet *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
device msubcircuit plowvt pfetlvt *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
device msubcircuit phighvt pfethvt *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
device msubcircuit nshort nfet *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
device msubcircuit nlowvt nfetlvt *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
device msubcircuit sonos_p nsonos *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
device subcircuit xcnwvc varactor *nndiff nwell error l=l w=w
device subcircuit xcnwvc2 varhvt *nndiff nwell error l=l w=w
device msubcircuit phv mvpfet *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w
device msubcircuit nhv mvnfet *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
device msubcircuit nhv_native mvnnfet *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
device subcircuit xchvnwc mvvaractor *mvnndiff nwell error l=l w=w
device rsubcircuit mrl1 rli1 *li pwell,space/w,nwell error l=l w=w
device rsubcircuit mrm1 rmetal1 *metal1 space/w,pwell,nwell error l=l w=w
device rsubcircuit mrm2 rmetal2 *metal2 space/w,pwell,nwell error l=l w=w
device rsubcircuit mrm3 rmetal3 *metal3 space/w,pwell,nwell error l=l w=w
device rsubcircuit mrm4 rm4 *m4 space/w,pwell,nwell error l=l w=w
device rsubcircuit mrm5 rm5 *m5 space/w,pwell,nwell error l=l w=w
device rsubcircuit xhrpoly xhrpoly *poly pwell,space/w error l=l w=w
device rsubcircuit mrp1 mrp1 *poly pwell,space/w error l=l w=w
device rsubcircuit mrdn ndiffres *ndiff pwell,space/w error l=l w=w
device rsubcircuit mrdp pdiffres *pdiff nwell error l=l w=w
device rsubcircuit xpwres rpw *psd dnwell error l=l w=w
device rsubcircuit mrdn_hv mvndiffres *mvndiff pwell,space/w error l=l w=w
device rsubcircuit mrdp_hv mvpdiffres *mvpdiff nwell error l=l w=w
device subcircuit pdiode *pdiode nwell a=area
device msubcircuit ndiode *ndiode pwell,space/w a=area
device msubcircuit ndiode_lvt *ndiodelvt pwell,space/w a=area
device msubcircuit ndiode_native *nndiode nwell a=area
device subcircuit pdiode_lvt *pdiodelvt nwell a=area
device subcircuit pdiode_hvt *pdiodehvt nwell a=area
device subcircuit pdiode_h *mvpdiode nwell a=area
device msubcircuit ndiode_h *mvndiode pwell,space/w a=area
device subcircuit xcmim1 *mimcap *m3 space/w,pwell,nwell error a=a p=p
device subcircuit xcmim2 *mimcap2 *m4 space/w,pwell,nwell error a=a p=p
variant (lvs)
device mosfet pshort pfet pdiff,pdiffres,pdc nwell
device mosfet plowvt pfetlvt pdiff,pdiffres,pdc nwell
device mosfet phighvt pfethvt pdiff,pdiffres,pdc nwell
device mosfet nshort nfet ndiff,ndiffres,ndc pwell,space/w
device mosfet nlowvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
device mosfet sonos_p nsonos ndiff,ndiffres,ndc pwell,space/w
device mosfet xcnwvc varactor *nndiff nwell
device mosfet phv mvpfet mvpdiff,mvpdiffres,mvpdc nwell
device mosfet hnv mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
device mosfet xchvnwc mvvaractor *mvnndiff nwell
device resistor mli1 rli1 *li
device resistor mrm1 rmetal1 *metal1
device resistor mrm2 rmetal2 *metal2
device resistor mrm3 rmetal3 *metal3
device resistor mrm4 rm4 *m4
device resistor mrm5 rm5 *m5
device resistor xhrpoly xhrpoly *poly
device resistor mrp1 mrp1 *poly
device resistor mrdn ndiffres *ndiff
device resistor mrdp pdiffres *pdiff
device resistor mrdn_hv mvndiffres *mvndiff
device resistor mrdp_hv mvpdiffres *mvpdiff
device resistor xpwres rpw *psd
device pdiode pdiode *pdiode nwell a=area
device ndiode ndiode *ndiode pwell,space/w a=area
device ndiode ndiode_native *nndiode nwell a=area
device pdiode pdiode_h *mvpdiode nwell a=area
device ndiode ndiode_h *mvndiode pwell,space/w a=area
device subcircuit xcmim1 *mimcap *m3 space/w,pwell,nwell error a=a p=p
device subcircuit xcmim2 *mimcap2 *m4 space/w,pwell,nwell error a=a p=p
end
#-----------------------------------------------------
# Wiring tool definitions
#-----------------------------------------------------
wiring
contact v1 16 m1 1 m2 0
contact v2 16 m2 1 m3 0
contact v3 18 m3 0 m4 4
contact v4 18 m4 0 m5 4
contact lic 14 li 0 m1 0
end
#-----------------------------------------------------
# Plain old router. . .
#-----------------------------------------------------
router
end
#------------------------------------------------------------
# Plowing (restored in magic 8.2, need to fill this section)
#------------------------------------------------------------
plowing
end
#-----------------------------------------------------------------
# No special plot layers defined (use default PNM color choices)
#-----------------------------------------------------------------
plot
style pnm
default
draw fillblock no_color_at_all
draw nwell cwell
end