sky130_fd_sc_hd high density standard cell libraryThis directory contains symbols to be used in the XSCHEM schematic editor. For a quick XSCHEM introduction see this presentation.
These symbols represent a tentative list of digital logic standard cells to be used to build digital circuit schematics in XSCHEM.
The list is based on the google skywater repository These symbols should bind correctly (same port order, same power pins) with the respective spice netlists available in the skywater repository.
Provide a set of digital logic gates that can be used with xschem and seamlessly simulated using the Skywater 130 PDK simulation SPICE models. Allowing verilog simulation directly from Xschem is another goal.
The gates can be placed in a XSCHEM schematic and a valid spice netlist is generated for them. you must however include the spice netlists for all the used digital gates. Below a simple trivial example of a combinatorial gate and a flip-flop simulated with ngspice.
