commit 8b9c8ffd581b4dcaa6b8a038c2b4b2ab11408b09
author VrushabhDamle <89193562+VrushabhDamle@users.noreply.github.com> Fri Dec 30 21:52:41 2022 +0530
committer GitHub <noreply@github.com> Fri Dec 30 21:52:41 2022 +0530
tree 2470b1d3133b13bd81ff719251e8a83902a7d53d
parent fd5fb780951c099c391b07f4140ffb945a733b93

Update config.json

openlane/user_project_wrapper/config.json

diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 22a00ee..8970d87 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -2,13 +2,13 @@
     "DESIGN_NAME": "user_project_wrapper",
     "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v"],
     "CLOCK_PERIOD": 10,
-    "CLOCK_PORT": "user_clock2",
+    "CLOCK_PORT": "wb_clk_i",
     "CLOCK_NET": "mprj.clk",
     "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
     "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
-    "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
-    "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
-    "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
+    "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/cla.v"],
+    "EXTRA_LEFS": "dir::../../lef/cla.lef",
+    "EXTRA_GDS_FILES": "dir::../../gds/cla.gds",
     "FP_PDN_CHECK_NODES": 0,
     "SYNTH_ELABORATE_ONLY": 1,
     "PL_RANDOM_GLB_PLACEMENT": 1,