commit 4d5f066660476fc9bf80c047e8113375a96540cb
author Thorsten Knoll <thorsten_knoll@yahoo.de> Sat Dec 31 19:55:32 2022 +0000
committer Thorsten Knoll <thorsten_knoll@yahoo.de> Sat Dec 31 19:55:32 2022 +0000
tree c6cd697fb9e1754083d7bbd2bf072afb58f58a00
parent 8d130d5568d3e1919f90734b583f032ffdaa4dc3

update config.json

openlane/tiny_user_project/config.json

diff --git a/openlane/tiny_user_project/config.json b/openlane/tiny_user_project/config.json
index a521e86..52b6277 100644
--- a/openlane/tiny_user_project/config.json
+++ b/openlane/tiny_user_project/config.json
@@ -2,7 +2,7 @@
     "DESIGN_NAME": "tiny_user_project",
     "DESIGN_IS_CORE": 0,
     "VERILOG_FILES": [
-        "dir::../../verilog/rtl/user_module.v",
+        "dir::../../verilog/rtl/vga_clock.v",
         "dir::../../verilog/rtl/cells.v",
         "dir::../../verilog/rtl/defines.v",
         "dir::../../verilog/rtl/tiny_user_project.v"
@@ -11,7 +11,7 @@
     "CLOCK_PORT": "io_in[0]",
     "CLOCK_NET": "io_in[0]",
     "FP_SIZING": "absolute",
-    "DIE_AREA": "0 0 150 170",
+    "DIE_AREA": "0 0 250 270",
     "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",    
     "PL_BASIC_PLACEMENT": 1,
     "PL_TARGET_DENSITY": 0.7,