tree: 2e0ce3b523e5a2e36dcebe23610bba962320e5da [path history] [tgz]
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. mpw_precheck/
  9. openlane/
  10. signoff/
  11. spi/
  12. tapeout/
  13. verilog/
  14. .gitignore
  15. LICENSE
  16. Makefile
  17. README.md
README.md

Caravel User Project

This project simulates a synchronous FIFO where data is written in a sequential manner into a memory buffer using a clock signal, and the data is read out in the same manner as it was entered from the memory array using the same clock signal.