commit 3b0693f58ba1b88df802ff253f63f97b3ed32d07
author majilokesh <72696170+majilokesh@users.noreply.github.com> Tue Dec 06 13:50:51 2022 +0530
committer GitHub <noreply@github.com> Tue Dec 06 13:50:51 2022 +0530
tree 713736aaf3662683f3781b7d5884b4d46aa84db0
parent 13a5614dca5a9ce7551c7e0d82451d20ac772a51

Update config.json

openlane/user_proj_example/config.json

diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
index 370d74c..95f11ab 100644
--- a/openlane/user_proj_example/config.json
+++ b/openlane/user_proj_example/config.json
@@ -2,7 +2,7 @@
     "DESIGN_NAME": "user_proj_example",
     "DESIGN_IS_CORE": 0,
     "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
-    "CLOCK_PERIOD": 10,
+    "CLOCK_PERIOD": 20,
     "CLOCK_PORT": "wb_clk_i",
     "CLOCK_NET": "counter.clk",
     "FP_SIZING": "absolute",
@@ -18,20 +18,20 @@
         "FP_CORE_UTIL": 45,
         "RT_MAX_LAYER": "met4",
         "scl::sky130_fd_sc_hd": {
-            "CLOCK_PERIOD": 10
+            "CLOCK_PERIOD": 20
         },
         "scl::sky130_fd_sc_hdll": {
-            "CLOCK_PERIOD": 10
+            "CLOCK_PERIOD": 20
         },
         "scl::sky130_fd_sc_hs": {
-            "CLOCK_PERIOD": 8
+            "CLOCK_PERIOD": 18
         },
         "scl::sky130_fd_sc_ls": {
-            "CLOCK_PERIOD": 10,
+            "CLOCK_PERIOD": 20,
             "SYNTH_MAX_FANOUT": 5
         },
         "scl::sky130_fd_sc_ms": {
-            "CLOCK_PERIOD": 10
+            "CLOCK_PERIOD": 20
         }
     },
     "pdk::gf180mcuC": {
@@ -42,4 +42,4 @@
         "SYNTH_MAX_FANOUT": 4,
         "PL_TARGET_DENSITY": 0.45
     }
-}
\ No newline at end of file
+}