commit 13a5614dca5a9ce7551c7e0d82451d20ac772a51
author majilokesh <72696170+majilokesh@users.noreply.github.com> Sat Dec 03 12:43:42 2022 +0530
committer GitHub <noreply@github.com> Sat Dec 03 12:43:42 2022 +0530
tree b677433ca89cfb8bd98dde1e2782ad25c7d42571
parent bc50ce34e18dfbcbc561f36c0ca10f3f5def9123

Update user_proj_example.v

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 5ca3035..f90ca91 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -103,7 +103,9 @@
     assign io_out[35:33] = light_highway;
     assign io_out[32:30] = light_farm;
     assign io_oeb = 0;
-    assign {clk,rst_n,C} = io_in[`MPRJ_IO_PADS-9:`MPRJ_IO_PADS-7]; 
+    assign clk = wb_clk_i;
+    assign rst_n = wb_rst_i;
+    assign C = io_in[`MPRJ_IO_PADS-9]; 
     //assign io_out = count;
     //assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};