1402fdb655d786a09b790818f91840bd8987df60 - third_party/shuttle/sky130/mpw-008/slot-025

commit	1402fdb655d786a09b790818f91840bd8987df60	[log] [tgz]
author	urielcho <uriel.jaramillo@cinvestav.mx>	Fri Dec 23 13:28:54 2022 -0600
committer	urielcho <uriel.jaramillo@cinvestav.mx>	Fri Dec 23 13:28:54 2022 -0600
tree	52fce74ac902419d38fdb4823e0fc74d01457454
parent	f6684280c091719ffe1c185801a63c3fe3f8a4bf [diff]

Add existing file

gds/OQPSK_PS_RCOSINE2.gds[Added - diff]
gds/OQPSK_RCOSINE_ALL.gds[Added - diff]
gds/Top_Module_4_ALU.gds.gz[Added - diff]
gds/divider.gds[Added - diff]
gds/posoco2000.gds[Added - diff]
gds/user_proj_example.gds[Added - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
mag/OQPSK_PS_RCOSINE2.mag[Added - diff]
mag/OQPSK_RCOSINE_ALL.mag[Added - diff]
mag/Top_Module_4_ALU.mag.gz[Added - diff]
mag/divider.mag[Added - diff]
mag/posoco2000.mag[Added - diff]
mag/user_proj_example.mag[Added - diff]
mag/user_project_wrapper.mag[Added - diff]
spef/OQPSK_PS_RCOSINE2.spef[Added - diff]
spef/OQPSK_RCOSINE_ALL.spef[Added - diff]
spef/Top_Module_4_ALU.spef.gz[Added - diff]
spef/divider.spef[Added - diff]
spef/multicorner/user_project_wrapper.max.spef[Added - diff]
spef/multicorner/user_project_wrapper.min.spef[Added - diff]
spef/multicorner/user_project_wrapper.nom.spef[Added - diff]
spef/posoco2000.spef[Added - diff]
spef/user_proj_example.spef[Added - diff]
spef/user_project_wrapper.spef[Added - diff]
verilog/dv/Makefile[Added - diff]
verilog/dv/README.md[Added - diff]
verilog/dv/io_ports/Makefile[Added - diff]
verilog/dv/io_ports/io_ports.c[Added - diff]
verilog/dv/io_ports/io_ports_tb.v[Added - diff]
verilog/dv/la_test1/Makefile[Added - diff]
verilog/dv/la_test1/la_test1.c[Added - diff]
verilog/dv/la_test1/la_test1_tb.v[Added - diff]
verilog/dv/la_test2/Makefile[Added - diff]
verilog/dv/la_test2/la_test2.c[Added - diff]
verilog/dv/la_test2/la_test2_tb.v[Added - diff]
verilog/dv/local-install.md[Added - diff]
verilog/dv/mprj_stimulus/Makefile[Added - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Added - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Added - diff]
verilog/dv/wb_port/Makefile[Added - diff]
verilog/dv/wb_port/wb_port.c[Added - diff]
verilog/dv/wb_port/wb_port_tb.v[Added - diff]
verilog/gl/OQPSK_PS_RCOSINE2.nl.v[Added - diff]
verilog/gl/OQPSK_PS_RCOSINE2.v[Added - diff]
verilog/gl/OQPSK_RCOSINE_ALL.nl.v[Added - diff]
verilog/gl/OQPSK_RCOSINE_ALL.v[Added - diff]
verilog/gl/Top_Module_4_ALU.nl.v[Added - diff]
verilog/gl/Top_Module_4_ALU.v[Added - diff]
verilog/gl/divider.nl.v[Added - diff]
verilog/gl/divider.v[Added - diff]
verilog/gl/posoco2000.nl.v[Added - diff]
verilog/gl/posoco2000.v[Added - diff]
verilog/gl/user_proj_example.nl.v[Added - diff]
verilog/gl/user_proj_example.v[Added - diff]
verilog/gl/user_project_wrapper.nl.v[Added - diff]
verilog/gl/user_project_wrapper.v[Added - diff]
verilog/includes/includes.gl+sdf.caravel_user_project[Added - diff]
verilog/includes/includes.gl.caravel_user_project[Added - diff]
verilog/includes/includes.rtl.caravel_user_project[Added - diff]
verilog/rtl/OQPSK_PS_RCOSINE2.v[Added - diff]
verilog/rtl/OQPSK_RCOSINE_ALL.v[Added - diff]
verilog/rtl/Top_Module_4_ALU.v[Added - diff]
verilog/rtl/defines.v[Added - diff]
verilog/rtl/divider.v[Added - diff]
verilog/rtl/posoco2000.v[Added - diff]
verilog/rtl/uprj_netlists.v[Added - diff]
verilog/rtl/user_defines.v[Added - diff]
verilog/rtl/user_proj_example.v[Added - diff]
verilog/rtl/user_project_wrapper.v[Added - diff]

69 files changed

tree: 52fce74ac902419d38fdb4823e0fc74d01457454

README.md

This is the comparison project of the projects of the CINVESTAV GUADALAJARA community.

The 180 and 130 nm technologies in the GFMPW-0 and SKYMPW-8 are compared.

This project includes an ALU, a divider, a 7-segment display controller, a synchronous modulator, and an asynchronous modulator.