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foss-eda-tools
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third_party
/
shuttle
/
sky130
/
mpw-008
/
slot-024
/
014204425607cc32b9d26b35a2963a7632ee35ca
commit
014204425607cc32b9d26b35a2963a7632ee35ca
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log
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tgz
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author
Marwan Abbas <marwaneltoukhy@aucegypt.edu>
Thu Jul 07 18:48:40 2022 +0200
committer
Marwan Abbas <marwaneltoukhy@aucegypt.edu>
Thu Jul 07 18:48:40 2022 +0200
tree
aa4d41fdb43a7e558a9db561e110b2699e040ef8
parent
030623058a178917e2752bb29a5a16b426ec5691
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added PDK variable
.github/workflows/user_project_ci.yml
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Makefile
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mag/example_por.mag
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mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
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mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
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mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
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mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
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mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
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mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
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mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
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mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
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mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
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mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
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mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
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mag/user_analog_proj_example.mag
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mag/user_analog_project_wrapper.mag
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mag/user_analog_project_wrapper_empty.mag
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netgen/run_lvs_por.sh
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netgen/run_lvs_wrapper_verilog.sh
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netgen/run_lvs_wrapper_xschem.sh
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verilog/dv/README.md
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verilog/dv/mprj_por/Makefile
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22 files changed
tree: aa4d41fdb43a7e558a9db561e110b2699e040ef8
.github/
docs/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
caravel
.gitignore
LICENSE
Makefile
README.md
README.md
Caravel Analog User
:exclamation: Important Note
Please fill in your project documentation in this README.md file
:warning:
Use this sample project for analog user projects.
Refer to
README
for this sample project documentation.
