Update wb_port.c

add def for reg_mprj_slave

verilog/dv/wb_port/wb_port.c

diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index e649f7c..c9c6996 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -19,6 +19,8 @@
 #include <defs.h>
 #include <stub.c>
 
+#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+
 /*
 	Wishbone Test:
 		- Configures MPRJ lower 8-IO pins as outputs