changed docker image to use dv for CVC
NOTE: Added testbenches will FAIL
added testbenches to configure the io in different modes:
- io_ports_bid: bidirectional
- io_ports_bid_gpio: bidirectional with only gpio_control_block
sdf_annotation
- io_ports_bid_nosdf: bidirectional with no sdf_annotation
- io_ports_nopull: input nopull
- io_ports_pulldown: input pulldown
- io_ports_pullup: input pullup
diff --git a/Makefile b/Makefile
index e787f93..6719339 100644
--- a/Makefile
+++ b/Makefile
@@ -74,19 +74,18 @@
dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf)
TARGET_PATH=$(shell pwd)
-verify_command="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+verify_command="source ~/.bashrc && cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
dv_base_dependencies=simenv
docker_run_verify=\
docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
-v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
-e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
-e CARAVEL_ROOT=${CARAVEL_ROOT} \
- -e TOOLS=/opt/riscv32i \
+ -e TOOLS=/foss/tools/riscv-gnu-toolchain-rv32i/217e7f3debe424d61374d31e33a091a630535937 \
-e DESIGNS=$(TARGET_PATH) \
-e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \
- -e GCC_PREFIX=riscv32-unknown-elf \
-e MCW_ROOT=$(MCW_ROOT) \
- -u $$(id -u $$USER):$$(id -g $$USER) efabless/dv_setup:latest \
+ -u $$(id -u $$USER):$$(id -g $$USER) efabless/dv:latest \
sh -c $(verify_command)
.PHONY: harden
