Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-008
/
slot-020
/
340cc4a6a8be1caf0eac97c099105ec9f9ed8165
/
verilog
/
dv
/
mprj_stimulus
340cc4a
Update full chip simulation to run from root
by manarabdelaty
· 4 years ago
22f3cd0
Submodule caravel-lite
by manarabdelaty
· 4 years ago
c0f458a
Update DV Makefile
by manarabdelaty
· 4 years ago
eac56e8
Rename CARAVEL_MASTER -> CARAVEL_ROOT
by manarabdelaty
· 4 years ago
8dbabc1
Update DV Makefiles
by manarabdelaty
· 4 years ago
f989c64
Corrected the user_project_wrapper verilog to have the correct
by Tim Edwards
· 4 years ago
a7929f3
Added mprj_stimulus test
by manarabdelaty
· 4 years ago