| commit | d79dc5b415ad859453cb54f72d28b4be2cc94735 | [log] [tgz] |
|---|---|---|
| author | Ruige <295054118@whut.edu.cn> | Fri Nov 25 19:38:58 2022 +0800 |
| committer | Ruige <295054118@whut.edu.cn> | Fri Nov 25 19:38:58 2022 +0800 |
| tree | 2f824cb289b11e23401abb07100d02cac9ffe701 | |
| parent | dd23884f7ac5d388e4e2bfeb2c1cd1edc5f8bab3 [diff] |
submit for Rift2320_Sky130_MPW8 Signed-off-by: Ruige <295054118@whut.edu.cn>
This is a simple version of Rift2Core. Commit: b95a1555aeb79d975e8b273d412f0e6df42d0322 (Almost...)
The configuration is as followed:
class Rift2320 extends Config((site, here, up) => {
case RiftParamsKey => RiftSetting(
hasL2 = true,
hasDebugger = true,
hasPreFetch = false,
hasuBTB = false,
ftChn = 4,
rnChn = 1,
opChn = 2,
wbChn = 1,
cm_chn = 1,
pmpNum = 0,
regNum = 34,
hpmNum = 0,
l1BeatBits = 64,
memBeatBits = 64,
tlbEntry = 2,
l1DW = 128,
ifetchParameters = IFParameters(
uBTB_entry = 4,
btb_cl = 4,
bim_cl = 8,
ras_dp = 4,
),
icacheParameters = IcacheParameters(
bk = 1,
cb = 2,
cl = 4,
),
dcacheParameters = DcacheParameters(
bk = 1,
cb = 2,
cl = 4,
sbEntry = 2,
stEntry = 2,
),
dptEntry = 4,
fpuNum = 0,
mulNum = 1,
isMinArea = true,
isLowPower = false,
)
})