Merge pull request #194 from proppy/fix-gf180mcu-template
openlane/user_project_wrapper_gf180mcu: remove components and nets section
diff --git a/Makefile b/Makefile
index 5842df0..7a99ad4 100644
--- a/Makefile
+++ b/Makefile
@@ -33,8 +33,8 @@
ifeq ($(PDK),sky130A)
SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
- export OPENLANE_TAG?=2022.10.20
- MPW_TAG ?= mpw-7d
+ export OPENLANE_TAG?=2022.11.19
+ MPW_TAG ?= mpw-8a
ifeq ($(CARAVEL_LITE),1)
CARAVEL_NAME := caravel-lite
@@ -51,8 +51,8 @@
ifeq ($(PDK),sky130B)
SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
- export OPENLANE_TAG?=2022.10.20
- MPW_TAG ?= mpw-7d
+ export OPENLANE_TAG?=2022.11.19
+ MPW_TAG ?= mpw-8a
ifeq ($(CARAVEL_LITE),1)
CARAVEL_NAME := caravel-lite
@@ -74,7 +74,7 @@
CARAVEL_TAG := $(MPW_TAG)
#OPENLANE_TAG=ddfeab57e3e8769ea3d40dda12be0460e09bb6d9
export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
- export OPENLANE_TAG?=2022.11.17
+ export OPENLANE_TAG?=2022.11.19
endif
@@ -264,7 +264,7 @@
export CUP_ROOT=$(shell pwd)
export TIMING_ROOT?=$(shell pwd)/deps/timing-scripts
export PROJECT_ROOT=$(CUP_ROOT)
-timing-scripts-repo=git@github.com:efabless/timing-scripts.git
+timing-scripts-repo=https://github.com/efabless/timing-scripts.git
$(TIMING_ROOT):
@mkdir -p $(CUP_ROOT)/deps
diff --git a/docs/source/index.rst b/docs/source/index.rst
index 36127a7..de1083e 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -32,12 +32,14 @@
- `Repo Integration <#repo-integration>`__
- `Verilog Integration <#verilog-integration>`__
+ - `GPIO Configuration <#gpio-configuration>`__
- `Layout Integration <#layout-integration>`__
- `Running Full Chip Simulation <#running-full-chip-simulation>`__
- `User Project Wrapper Requirements <#user-project-wrapper-requirements>`__
- `Hardening the User Project using
Openlane <#hardening-the-user-project-using-openlane>`__
+- `Running Timing Analysis on Existing Projects <#running-timing-analysis-on-existing-projects>`__
- `Checklist for Open-MPW
Submission <#checklist-for-open-mpw-submission>`__
@@ -247,6 +249,40 @@
</p>
+-------------------
+GPIO Configuration
+-------------------
+
+You are required to specify the power-on default configuration for each GPIO in Caravel. The default configuration provide the state the GPIO will come up on power up. The configuration can be changed by the management SoC during firmware execution.
+
+Configuration settings define whether the GPIO is configured to connect to the user project area or the managment SoC. They also determine whether IOs are inputs or outputs, digital or analog, as well as whether pull-up or pull-down resistors are configured for inputs.
+
+GPIOs are configured by assigning predefined values for each IO in the file `verilog/rtl/user_defines.v <https://github.com/efabless/caravel_user_project/blob/main/verilog/rtl/user_defines.v>`_ in your project.
+
+You need to assigned configuration values for GPIO[5] thru GPIO[37].
+
+GPIO[0] thru GPIO[4] are preset and cannot be changed.
+
+The following values are redefined for assigning to GPIOs.
+
+
+- GPIO_MODE_MGMT_STD_INPUT_NOPULL
+- GPIO_MODE_MGMT_STD_INPUT_PULLDOWN
+- GPIO_MODE_MGMT_STD_INPUT_PULLUP
+- GPIO_MODE_MGMT_STD_OUTPUT
+- GPIO_MODE_MGMT_STD_BIDIRECTIONAL
+- GPIO_MODE_MGMT_STD_ANALOG
+
+- GPIO_MODE_USER_STD_INPUT_NOPULL
+- GPIO_MODE_USER_STD_INPUT_PULLDOWN
+- GPIO_MODE_USER_STD_INPUT_PULLUP
+- GPIO_MODE_USER_STD_OUTPUT
+- GPIO_MODE_USER_STD_BIDIRECTIONAL
+- GPIO_MODE_USER_STD_OUT_MONITORED
+- GPIO_MODE_USER_STD_ANALOG
+
+
+MPW_Prececk includes a check to confirm each GPIO is assigned a valid value.
-------------------
Layout Integration
@@ -457,6 +493,38 @@
This will run all the precheck checks on your project and will produce the logs under the ``checks`` directory.
+Running Timing Analysis on Existing Projects
+========================================================
+
+Start by updating the Makefile for your project. Starting in the project root...
+
+.. code:: bash
+
+ curl -k https://raw.githubusercontent.com/efabless/caravel_user_project/main/Makefile > Makefile
+
+ make setup-timing-scripts
+
+ make install
+
+ make install_mcw
+
+
+This will update Caravel design files and install the scripts for running timing.
+
+
+Then, you can run then run timing by the following...
+
+.. code:: bash
+
+ make extract-parasitics
+
+ make create-spef-mapping
+
+ make caravel-sta
+
+
+A summary of timing results is provided at the end of the flow.
+
Other Miscellaneous Targets
============================
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 388070c..22a00ee 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -17,8 +17,8 @@
"PL_RESIZER_BUFFER_INPUT_PORTS": 0,
"FP_PDN_ENABLE_RAILS": 0,
"DIODE_INSERTION_STRATEGY": 0,
- "FILL_INSERTION": 0,
- "TAP_DECAP_INSERTION": 0,
+ "RUN_FILL_INSERTION": 0,
+ "RUN_TAP_DECAP_INSERTION": 0,
"FP_PDN_VPITCH": 180,
"FP_PDN_HPITCH": 180,
"CLOCK_TREE_SYNTH": 0,
@@ -27,7 +27,7 @@
"MAGIC_ZEROIZE_ORIGIN": 0,
"FP_SIZING": "absolute",
"RUN_CVC": 0,
- "UNIT": 2.4,
+ "UNIT": "2.4",
"FP_IO_VEXTEND": "expr::2 * $UNIT",
"FP_IO_HEXTEND": "expr::2 * $UNIT",
"FP_IO_VLENGTH": "ref::$UNIT",
@@ -82,4 +82,4 @@
"MAGIC_WRITE_FULL_LEF": 0,
"FP_PDN_ENABLE_RAILS": 0
}
-}
\ No newline at end of file
+}
