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slot-019
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5178fa03e6c57b9c613a0df576956070f240d270
commit
5178fa03e6c57b9c613a0df576956070f240d270
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tgz
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author
andylithia <thelithcore@gmail.com>
Sun Jan 01 02:11:58 2023 -0500
committer
andylithia <thelithcore@gmail.com>
Sun Jan 01 02:11:58 2023 -0500
tree
5068355f05aad1c1fcc3d7b7c4556e42b42ad0e3
parent
860f712118e681e3d0672591ff36bd88bdc729ae
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diff
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DRC fix, passes pre-check
gds/user_analog_project_wrapper.gds
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diff
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netgen/user_analog_project_wrapper.spice
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diff
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verilog/rtl/user_defines.v
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diff
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3 files changed
tree: 5068355f05aad1c1fcc3d7b7c4556e42b42ad0e3
.github/
docs/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
caravel
.gitignore
LICENSE
Makefile
README.md
README.md
Caravel Analog User
This is initial readme