commit: ff14a076c4b0c667f104775626ae97706aca5740
[log]
author: dineshannayya <dinesh.annayya@gmail.com>
Sun Dec 25 14:56:02 2022 +0530
committer: dineshannayya <dinesh.annayya@gmail.com>
Sun Dec 25 14:56:02 2022 +0530
tree: a5d5e670b448dcd850c314737ccb822dc842c94c
parent: ed072745c6e1fa9d5dd3cc6ae5d5a1877395b122 [diff]

mac core integrated

gds/user_project_wrapper.gds.gz[diff]
lef/user_project_wrapper.lef.gz[diff]
openlane/glbl_cfg/pdn.tcl[Deleted - diff]
openlane/glbl_cfg/pin_order.cfg[Deleted - diff]
openlane/mac_wrapper/base.sdc[Added - diff]
openlane/mac_wrapper/config.tcl[Added - diff]
openlane/mac_wrapper/pin_order.cfg[Added - diff]
openlane/mbist_top1/base.sdc[Deleted - diff]
openlane/mbist_top1/pin_order.cfg[Deleted - diff]
openlane/mbist_top2/base.sdc[Deleted - diff]
openlane/mbist_top2/config.tcl[Deleted - diff]
openlane/mbist_top2/pin_order.cfg[Deleted - diff]
openlane/mbist_top2/sta.tcl[Deleted - diff]
openlane/mbist_wrapper/base.sdc[Added - diff]
openlane/mbist_wrapper/config.tcl[Renamed from openlane/mbist_top1/config.tcl - diff]
openlane/mbist_wrapper/pin_order.cfg[Added - diff]
openlane/mbist_wrapper/sta.tcl[Renamed from openlane/mbist_top1/sta.tcl - diff]
openlane/pinmux_top/base.sdc[Renamed from openlane/glbl_cfg/base.sdc - diff]
openlane/pinmux_top/config.tcl[Renamed from openlane/glbl_cfg/config.tcl - diff]
openlane/pinmux_top/pin_order.cfg[Added - diff]
openlane/scripts/scan_connect.tcl[Added - diff]
openlane/scripts/scan_swap.tcl[Added - diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
openlane/wb_host/base.sdc[diff]
openlane/wb_host/config.tcl[diff]
openlane/wb_host/pin_order.cfg[diff]
openlane/wb_interconnect/base.sdc[diff]
openlane/wb_interconnect/config.tcl[diff]
openlane/wb_interconnect/pin_order.cfg[diff]
sdc/caravel.sdc[Added - diff]
sdc/glbl_cfg.sdc[Added - diff]
sdc/mac_wrapper.sdc[Added - diff]
sdc/mbist_top1.sdc[Added - diff]
sdc/mbist_top2.sdc[Added - diff]
sdc/mbist_wrapper.sdc[Added - diff]
sdc/pinmux_top.sdc[Added - diff]
sdc/user_project_wrapper.sdc[Added - diff]
sdc/wb_host.sdc[Added - diff]
sdc/wb_interconnect.sdc[Added - diff]
sta/scripts/caravel_timing.tcl[Added - diff]
sta/slew.cap.fanout.vio.rpt[Added - diff]
sta/sta.log[Added - diff]
sta/unconstraints.rpt[Added - diff]
verilog/dv/Makefile[diff]
verilog/dv/common/agents/ethernet/filelist_tb.f[Added - diff]
verilog/dv/common/agents/ethernet/tb_eth_conf.v[Added - diff]
verilog/dv/common/agents/ethernet/tb_eth_defs.v[Added - diff]
verilog/dv/common/agents/ethernet/tb_eth_objs.v[Added - diff]
verilog/dv/common/agents/ethernet/tb_eth_pktgn.v[Added - diff]
verilog/dv/common/agents/ethernet/tb_eth_tasks.v[Added - diff]
verilog/dv/common/agents/ethernet/tb_eth_top.v[Added - diff]
verilog/dv/common/agents/ethernet/tb_mii.v[Added - diff]
verilog/dv/common/agents/ethernet/tb_rmii.v[Added - diff]
verilog/dv/common/agents/tb_glbl.v[Added - diff]
verilog/dv/regression.rpt[Added - diff]
verilog/dv/user_mac_test1/Makefile[Added - diff]
verilog/dv/user_mac_test1/user_mac_test1_tb.v[Added - diff]
verilog/dv/user_mbist_test1/user_mbist_test1_tb.v[diff]
verilog/dv/user_mbist_test2/Makefile[Added - diff]
verilog/dv/user_mbist_test2/user_mbist_test2_tb.v[Added - diff]
verilog/gl/user_project_wrapper.v.gz[diff]
verilog/includes/includes.rtl.caravel_user_project[diff]
verilog/rtl/glbl/src/glbl_cfg.sv[diff]
verilog/rtl/gmac/mac/g_rx_top.v[diff]
verilog/rtl/gmac/top/g_mac_top.v[diff]
verilog/rtl/lib/async_fifo.sv[diff]
verilog/rtl/lib/async_fifo.v[diff]
verilog/rtl/lib/async_fifo_th.sv[diff]
verilog/rtl/lib/async_wb.sv[diff]
verilog/rtl/lib/wb_rd_mem2mem.v[diff]
verilog/rtl/lib/wb_wr_mem2mem.v[diff]
verilog/rtl/mac_wrapper/src/mac_wrapper.sv[diff]
verilog/rtl/mbist/src/top/mbist_top.sv[diff]
verilog/rtl/mbist_wrapper/src/mbist_reg.sv[Added - diff]
verilog/rtl/mbist_wrapper/src/mbist_wb.sv[diff]
verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv[diff]
verilog/rtl/pinmux/src/pinmux.sv[Added - diff]
verilog/rtl/pinmux/src/pinmux_top.sv[diff]
verilog/rtl/uart/src/uart_core.sv[diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl/user_reg_map.v[diff]
verilog/rtl/wb_host/src/wb_host.sv[diff]
verilog/rtl/wb_interconnect/src/wb_interconnect.sv[diff]

84 files changed

tree: a5d5e670b448dcd850c314737ccb822dc842c94c

README.md

riscduino_pxt1

Riscduino Peripheral Extension Chip Set-1

Reference

turbo8051 https://opencores.org/projects/turbo8051
Julien OURY MPW Project https://github.com/JulienOury/ChristmasTreeController.git
opengfx430 https://github.com/olgirard/opengfx430
openMSP430 https://opencores.org/websvn/filedetails?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2FopenMSP430.pdf
slau049f https://www.ti.com/lit/ug/slau049f/slau049f.pdf
LT24 Card http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=68&No=892&PartNo=2#heading