sspi slave integrated + uart Master with Auto Baud Detect
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 9d7632d..6fdb1e8 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -48,6 +48,8 @@
//// 1.0 - 31th Dec 2022, Dinesh A ////
//// A. Bus repeater added ////
//// B. Glbl Register added with signature/revison ////
+//// C. SSPI Slave Integrated ////
+//// D. Uart Master with Auto Baud Detect Logic ////
//////////////////////////////////////////////////////////////////////
`default_nettype none
