commit	935817ae76b582bb323710cee433b93ebdf463ef	[log] [tgz]
author	cloudxcc <tobias@cloudx.cc>	Sun Dec 04 00:05:04 2022 +0100
committer	cloudxcc <tobias@cloudx.cc>	Sun Dec 04 00:05:04 2022 +0100
tree	433f4ca4c6cc96eec0a78d3aa9a18c32749d7a11
parent	bae93e078005210307b7530e53d4a0c060ed5c54 [diff]

release

README.md[diff]
gds/user_project_wrapper.gds.gz[Added - diff]
lef/user_project_wrapper.lef[diff]
mag/user_project_wrapper.mag[diff]
maglef/user_project_wrapper.mag[diff]
openlane/Makefile[diff]
openlane/user_project_wrapper/macro.cfg[diff]
verilog/rtl/ca.v[Added - diff]
verilog/rtl/cawb.v[Added - diff]
verilog/rtl/clock_gen_empty.v[Added - diff]
verilog/rtl/cubev_rv32imc_p3.v[Added - diff]
verilog/rtl/gpio.v[Added - diff]
verilog/rtl/mem/sky130_sram_1kbyte_1rw1r_32x256_8.v[Added - diff]
verilog/rtl/minisoc.v[Added - diff]
verilog/rtl/rb.v[Added - diff]
verilog/rtl/user_defines.v[diff]
verilog/rtl/user_defines_orig.v[Added - diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl/wavesync.v[Added - diff]

19 files changed

tree: 433f4ca4c6cc96eec0a78d3aa9a18c32749d7a11

README.md

OpenLane / Skywater130 project.

Testrun