| commit | 771697a7f9abbe97d249ea0680596556d6e2ca0e | [log] [tgz] |
|---|---|---|
| author | Po-Chun Huang <hpcalex@terpmail.umd.edu> | Fri Dec 16 07:26:31 2022 -0500 |
| committer | Po-Chun Huang <hpcalex@terpmail.umd.edu> | Fri Dec 16 07:26:31 2022 -0500 |
| tree | d8c2bc5d483cfe54f12ab614e63c62b2fe229bf1 | |
| parent | e765ebf48ea44c26986d8248a6ac5af4b04a4905 [diff] |
update spice netlist file
| :exclamation: Important Note |
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This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for device performance characterization, e.g. I-V, transient, R-ratio, and variations, and ReRAM simulation model verification. The goal is to design a low power ReRAM controller optimized for write/read latency, endurance, and power consumption based on the actual measurement results of sky130 ReRAM devices.
| :warning: | Use this sample project for analog user projects. |
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Refer to README for this sample project documentation.