commit df78965b9cdfef7ea5ac4df51ac2484b815a78b5
author t-sasatani <33111879+t-sasatani@users.noreply.github.com> Fri Dec 30 03:34:47 2022 +0900
committer t-sasatani <33111879+t-sasatani@users.noreply.github.com> Fri Dec 30 03:34:47 2022 +0900
tree fb1766dff19acb7a1403a799c73a42997eed9e5c
parent 23745ed8472f521e1f6bb44babf986f0f8ccbfa6
parent 6ddf811440c5ad686eae84562a2a18fb53c0c8e1

Merge branch 'main' of https://github.com/t-sasatani/clock_divide_select_4ch_tiny_user

openlane/tiny_user_project/config.json

diff --git a/openlane/tiny_user_project/config.json b/openlane/tiny_user_project/config.json
index 43a2604..9b7dcf5 100644
--- a/openlane/tiny_user_project/config.json
+++ b/openlane/tiny_user_project/config.json
@@ -8,8 +8,8 @@
         "dir::../../verilog/rtl/tiny_user_project.v"
     ],
     "CLOCK_TREE_SYNTH": 1,
-    "CLOCK_PORT": "io_in[0]",
-    "CLOCK_NET": "io_in[0]",
+    "CLOCK_PORT": "clk",
+    "CLOCK_NET": "clk",
     "FP_SIZING": "absolute",
     "DIE_AREA": "0 0 120 150",
     "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",