configured verilog and peripheral files
diff --git a/info.yaml b/info.yaml index 65e82e8..1dc370c 100644 --- a/info.yaml +++ b/info.yaml
@@ -1,7 +1,7 @@ --- # TinyTapeout project information project: - wokwi_id: 334445762078310996 # If using wokwi, set this to your project's ID + wokwi_id: 0 # If using wokwi, set this to your project's ID # source_files: # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here # - verilog/rtl/counter.v # - verilog/rtl/decoder.v @@ -14,33 +14,56 @@ # # This info will be automatically collected and used to make a datasheet for the chip. documentation: - author: "" # Your name + author: "Takuya Sasatani" # Your name discord: "" # Your discord handle - make sure to include the # part as well - title: "" # Project title - description: "" # Short description of what your project does - how_it_works: "" # Longer description of how the project works + title: "Clock divide and selecter" # Project title + description: "Generates multiple channels of clocks and outputs one of them based on input" # Short description of what your project does + how_it_works: "clock_X_division_factor defines clock_X (X = A, B, C, D). clock_selector selects output clock." # Longer description of how the project works how_to_test: "" # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed external_hw: "" # Describe any external hardware needed language: "wokwi" # other examples include Verilog, Amaranth, VHDL, etc - doc_link: "" # URL to longer form documentation, eg the README.md in your repository - clock_hz: 0 # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0. + doc_link: "https://github.com/t-sasatani/clock_divide_select_4ch_tiny_user" # URL to longer form documentation, eg the README.md in your repository + clock_hz: 1000000 # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0. picture: "" # relative path to a picture in your repository inputs: # a description of what the inputs do - clock - - reset - - none - - none - - none - - none - - none - - none + - clock_selector_bit0 + - clock_selector_bit1 + - clock_A_division_factor_bit0 + - clock_A_division_factor_bit0 + - clock_A_division_factor_bit0 + - clock_A_division_factor_bit1 + - clock_A_division_factor_bit2 + - clock_A_division_factor_bit3 + - clock_A_division_factor_bit4 + - clock_A_division_factor_bit5 + - clock_A_division_factor_bit6 + - clock_A_division_factor_bit7 + - clock_B_division_factor_bit0 + - clock_B_division_factor_bit1 + - clock_B_division_factor_bit2 + - clock_B_division_factor_bit3 + - clock_B_division_factor_bit4 + - clock_B_division_factor_bit5 + - clock_B_division_factor_bit6 + - clock_B_division_factor_bit7 + - clock_C_division_factor_bit0 + - clock_C_division_factor_bit1 + - clock_C_division_factor_bit2 + - clock_C_division_factor_bit3 + - clock_C_division_factor_bit4 + - clock_C_division_factor_bit5 + - clock_C_division_factor_bit6 + - clock_C_division_factor_bit7 + - clock_D_division_factor_bit0 + - clock_D_division_factor_bit1 + - clock_D_division_factor_bit2 + - clock_D_division_factor_bit3 + - clock_D_division_factor_bit4 + - clock_D_division_factor_bit5 + - clock_D_division_factor_bit6 + - clock_D_division_factor_bit7 + - enable outputs: - - segment a # a description of what the outputs do - - segment b - - segment c - - segment d - - segment e - - segment f - - segment g - - none + - clock_selected
diff --git a/openlane/tiny_user_project/config.json b/openlane/tiny_user_project/config.json index a521e86..d36f0c5 100644 --- a/openlane/tiny_user_project/config.json +++ b/openlane/tiny_user_project/config.json
@@ -8,11 +8,11 @@ "dir::../../verilog/rtl/tiny_user_project.v" ], "CLOCK_TREE_SYNTH": 1, - "CLOCK_PORT": "io_in[0]", - "CLOCK_NET": "io_in[0]", + "CLOCK_PORT": "clk", + "CLOCK_NET": "ref::$CLOCK_PORT", "FP_SIZING": "absolute", - "DIE_AREA": "0 0 150 170", - "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", + "DIE_AREA": "0 0 300 300", + "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", "PL_BASIC_PLACEMENT": 1, "PL_TARGET_DENSITY": 0.7, "SYNTH_READ_BLACKBOX_LIB": 1, @@ -40,7 +40,7 @@ }, "pdk::gf180mcuC": { "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", - "CLOCK_PERIOD": 24.0, + "CLOCK_PERIOD": 3, "RT_MAX_LAYER": "Metal4", "SYNTH_MAX_FANOUT": 4, "VDD_NETS": [ @@ -50,4 +50,4 @@ "vss" ] } -} +} \ No newline at end of file
diff --git a/openlane/tiny_user_project/pin_order.cfg b/openlane/tiny_user_project/pin_order.cfg index bcd2a8f..ce2730f 100644 --- a/openlane/tiny_user_project/pin_order.cfg +++ b/openlane/tiny_user_project/pin_order.cfg
@@ -1,121 +1,43 @@ #BUS_SORT -#NR +#W +io_in\[0\] +io_in\[1\] +io_in\[2\] +io_in\[3\] +clk +io_in\[4\] +io_in\[5\] +io_in\[6\] +io_in\[7\] +io_in\[8\] +io_in\[9\] +io_in\[10\] +io_in\[11\] +io_in\[12\] +io_in\[13\] +io_in\[14\] io_in\[15\] -io_out\[15\] -io_oeb\[15\] io_in\[16\] -io_out\[16\] -io_oeb\[16\] io_in\[17\] -io_out\[17\] -io_oeb\[17\] io_in\[18\] -io_out\[18\] -io_oeb\[18\] io_in\[19\] -io_out\[19\] -io_oeb\[19\] io_in\[20\] -io_out\[20\] -io_oeb\[20\] io_in\[21\] -io_out\[21\] -io_oeb\[21\] io_in\[22\] -io_out\[22\] -io_oeb\[22\] io_in\[23\] -io_out\[23\] -io_oeb\[23\] +io_in\[24\] +io_in\[25\] +io_in\[26\] +io_in\[27\] +io_in\[28\] +io_in\[29\] +io_in\[30\] +io_in\[31\] +io_in\[32\] +io_in\[33\] +io_in\[34\] +io_in\[35\] #E -io_in\[0\] -io_out\[0\] -io_oeb\[0\] -io_in\[1\] -io_out\[1\] -io_oeb\[1\] -io_in\[2\] -io_out\[2\] -io_oeb\[2\] -io_in\[3\] -io_out\[3\] -io_oeb\[3\] -io_in\[4\] -io_out\[4\] -io_oeb\[4\] -io_in\[5\] -io_out\[5\] -io_oeb\[5\] -io_in\[6\] -io_out\[6\] -io_oeb\[6\] -io_in\[7\] -io_out\[7\] -io_oeb\[7\] -io_in\[8\] -io_out\[8\] -io_oeb\[8\] -io_in\[9\] -io_out\[9\] -io_oeb\[9\] -io_in\[10\] -io_out\[10\] -io_oeb\[10\] -io_in\[11\] -io_out\[11\] -io_oeb\[11\] -io_in\[12\] -io_out\[12\] -io_oeb\[12\] -io_in\[13\] -io_out\[13\] -io_oeb\[13\] -io_in\[14\] -io_out\[14\] -io_oeb\[14\] - -#WR -io_in\[24\] -io_out\[24\] -io_oeb\[24\] -io_in\[25\] -io_out\[25\] -io_oeb\[25\] -io_in\[26\] -io_out\[26\] -io_oeb\[26\] -io_in\[27\] -io_out\[27\] -io_oeb\[27\] -io_in\[28\] -io_out\[28\] -io_oeb\[28\] -io_in\[29\] -io_out\[29\] -io_oeb\[29\] -io_in\[30\] -io_out\[30\] -io_oeb\[30\] -io_in\[31\] -io_out\[31\] -io_oeb\[31\] -io_in\[32\] -io_out\[32\] -io_oeb\[32\] -io_in\[33\] -io_out\[33\] -io_oeb\[33\] -io_in\[34\] -io_out\[34\] -io_oeb\[34\] -io_in\[35\] -io_out\[35\] -io_oeb\[35\] -io_in\[36\] -io_out\[36\] -io_oeb\[36\] -io_in\[37\] -io_out\[37\] -io_oeb\[37\] +out.*
diff --git a/verilog/rtl/tiny_user_project.v b/verilog/rtl/tiny_user_project.v index 2725e32..3cd49d2 100644 --- a/verilog/rtl/tiny_user_project.v +++ b/verilog/rtl/tiny_user_project.v
@@ -16,7 +16,7 @@ ); // pass input and output pins defined in user_defines.v -user_module_334445762078310996 mod ( +user_module mod ( io_in[15:8], io_out[23:16] );
diff --git a/verilog/rtl/user_module.v b/verilog/rtl/user_module.v index aea8267..b071f4f 100644 --- a/verilog/rtl/user_module.v +++ b/verilog/rtl/user_module.v
@@ -1,88 +1,56 @@ -/* Automatically generated from https://wokwi.com/projects/334445762078310996 */ -`default_nettype none +module user_module( + input wire clk, + input wire [34:0] io_in, + output wire out + ); + + reg [8:0] clock_counter_a = 9'b000000000; + reg [8:0] clock_counter_b = 9'b000000000; + reg [8:0] clock_counter_c = 9'b000000000; + reg [8:0] clock_counter_d = 9'b000000000; + reg [3:0] div_clock = 4'b0000; -module user_module_334445762078310996( - input [7:0] io_in, - output [7:0] io_out -); - wire net1 = 1'b1; - wire net2 = 1'b0; - wire net3; - wire net4; - wire net5; - wire net6; - wire net7; - wire net8 = 1'b1; - wire net9 = 1'b0; - wire net10; - wire net11; - wire net12 = 1'b1; - wire net13 = 1'b0; - wire net14; - wire net15 = 1'b1; - wire net16 = 1'b0; - wire net17; - wire net18 = 1'b0; - wire net19 = 1'b1; - wire net20; - wire net21 = 1'b1; - wire net22; - wire net23; - wire net24 = 1'b0; - wire net25 = 1'b0; + wire [7:0] clock_div_factor_a; + wire [7:0] clock_div_factor_b; + wire [7:0] clock_div_factor_c; + wire [7:0] clock_div_factor_d; + wire [1:0] clock_select; + wire enable; + wire clock_syn; + + assign clock_select = io_in[1:0]; + assign enable = io_in[34]; + assign clock_syn = (enable)? div_clock[clock_select]:0; + assign clock_div_factor_a = io_in[9:2]; + assign clock_div_factor_b = io_in[17:10]; + assign clock_div_factor_c = io_in[25:18]; + assign clock_div_factor_d = io_in[33:26]; + + + always @ (posedge clk) begin + clock_counter_a <= clock_counter_a + 1; + clock_counter_b <= clock_counter_b + 1; + clock_counter_c <= clock_counter_c + 1; + clock_counter_d <= clock_counter_d + 1; - and_cell gate1 ( - .a (net3) - ); - or_cell gate2 ( - - ); - xor_cell gate3 ( - - ); - nand_cell gate4 ( - .a (net4), - .b (net5), - .out (net6) - ); - not_cell gate5 ( - .in (net7), - .out (net5) - ); - buffer_cell gate6 ( - - ); - mux_cell mux1 ( - .a (net8), - .b (net9), - .sel (net10), - .out (net11) - ); - dff_cell flipflop1 ( - - ); - mux_cell mux2 ( - .a (net12), - .b (net13), - .sel (net10), - .out (net14) - ); - mux_cell mux3 ( - .a (net15), - .b (net16), - .sel (net10), - .out (net17) - ); - mux_cell mux4 ( - .a (net18), - .b (net19), - .sel (net10), - .out (net20) - ); - and_cell gate7 ( - .a (net22), - .b (net23), - .out (net4) - ); + if (clock_div_factor_a < clock_counter_a) begin + div_clock[0] <= ~div_clock[0]; + clock_counter_a <= 9'b000000000; + end + if (clock_div_factor_b < clock_counter_b) begin + div_clock[1] <= ~div_clock[1]; + clock_counter_b <= 9'b000000000; + end + if (clock_div_factor_c < clock_counter_c) begin + div_clock[2] <= ~div_clock[2]; + clock_counter_c <= 9'b000000000; + end + if (clock_div_factor_d < clock_counter_d) begin + div_clock[3] <= ~div_clock[3]; + clock_counter_d <= 9'b000000000; + end + end + + assign out = clock_syn; endmodule