commit	c2ffd7842a9ba6ecc7ac779113195871b5ecaa4c	[log] [tgz]
author	t-sasatani <33111879+t-sasatani@users.noreply.github.com>	Fri Dec 30 01:24:42 2022 +0900
committer	t-sasatani <33111879+t-sasatani@users.noreply.github.com>	Fri Dec 30 01:24:42 2022 +0900
tree	f1e58b5f175da3fbc71454fff074e349976ae0b9
parent	040c9eea2e9811f9617d0991d747e3e1e5d91a30 [diff]

tree: f1e58b5f175da3fbc71454fff074e349976ae0b9

README.md

Tiny User Project

Template for submitting TinyTapeout based projects to the Open MPW shuttle program.

Usage

Generate a new project based on this template.
Set GitHub Pages Sources as GitHub Actions.
If using Wokwi:
- Reuse or create a new Wokwi project.
- Edit info.yaml:
  - In project:
    - Update wokwi_id with the last component of the Wokwi URL.
  - In documentation:
    - Update inputs to document the input wire of your project.
    - Update outputs to document the output wire of your project.
If using Verilog:
- Add your HDL code in verilog/rtl/.
- Edit info.yaml:
  - In project:
    - Set wokwi_id to 0.
    - Uncomment and update top_module to match your top-level module.
    - Uncomment and list your Verilog sources in src_files (paths relative to the root of the repository).
  - In documentation:
    - Update inputs to document the input wire of your top-level module.
    - Update outputs to document the output wire of your top-level module.
Commit, push and check the workflow summary (if successful a new commit including the hardened files will be automatically created).
Submit your project github repository to the next Open MPW shuttle.