commit | e9f8aeff8e9cd4a6c3da52f8c41d228ed12d1e78 | [log] [tgz] |
---|---|---|
author | Mathis Salmen <mathis.salmen@matsal.de> | Tue Nov 29 15:51:06 2022 +0100 |
committer | Mathis Salmen <mathis.salmen@matsal.de> | Tue Nov 29 15:51:06 2022 +0100 |
tree | 64293d4a18a4a6fdfc8ca2acada0f57263bfc6d2 | |
parent | 90026dd0deed450a7e81046fd388fb0ac53e33b2 [diff] |
Re-harden, higher density
SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute up to 4 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.
The Verilog source files can be found in verilog/rtl
. These are converted from SystemVerilog via zachjs' sv2v, the original SystemVerilog source code is available here.