commit | 39279e5db787dad301c2d078125ea1f0badf632f | [log] [tgz] |
---|---|---|
author | Mathis Salmen <mathis.salmen@matsal.de> | Tue Nov 22 19:37:32 2022 +0100 |
committer | Mathis Salmen <mathis.salmen@matsal.de> | Tue Nov 22 19:37:32 2022 +0100 |
tree | 3ac0957b00e4fdcd4257fe2dc41ff0fe3c40aaaa | |
parent | 1f01ef34bdc46395c67fcf1955452d688bef35e5 [diff] |
Added SoomRV to repo
SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute up to 4 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.
The Verilog source files can be found in verilog/rtl
. These are converted from SystemVerilog via zachjs' sv2v, the original SystemVerilog source code is available here.