tree: 09708789b87536c6e221e8c474fd7621bf95f4a4 [path history] [tgz]
  1. Makefile
  2. README.md
  3. scan_controller.c
  4. scan_controller.hex
  5. scan_controller_la.gtkw
  6. scan_controller_tb.v
  7. test_scan_controller.py
verilog/dv/scan_controller_la/README.md

logic analyser test

run

./configure.py --update-caravel --limit 20 --test

before starting test