clarity on input and output traces
diff --git a/INFO.md b/INFO.md
index 454f2eb..a65fcf7 100644
--- a/INFO.md
+++ b/INFO.md
@@ -18,10 +18,11 @@
* Signal names are from the perspective of the scan chain driver.
* The desired project shall be called DUT (design under test)
-Assuming you want to update DUT at position 2 (0 indexed) with lowest 3 inputs high and fetch the output.
+Assuming you want to update DUT at position 2 (0 indexed) with inputs = 0x02 and then fetch the output.
+This design connects an inverter between each input and output.
* Set scan_select low so that the data is clocked into the scan flops (rather than from the design)
-* For the next 8 clocks, set scan_data_out to 0, 0, 0, 0, 0, 0, 1, 1
+* For the next 8 clocks, set scan_data_out to 0, 0, 0, 0, 0, 0, 1, 0
* Toggle scan_clk_out 16 times to deliver the data to the DUT
* Toggle scan_latch_en to deliver the data from the scan chain to the DUT
* Set scan_select high to set the scan flop's input to be from the DUT
@@ -30,6 +31,12 @@
+*Notes on understanding the trace*
+
+* There are large wait times between the latch and scan signals to ensure no hold violations across the whole chain. For the internal scan controller, these can be configured (see section on wait states below).
+* The input looks wrong (0x03) because the input is incremented by the test bench as soon as the scan controller captures the data. The input is actually 0x02.
+* The output in the trace looks wrong (0xFE) because it's updated after a full refresh, the output is 0xFD.
+
## Clocking
Assuming:
