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diff --git a/verilog/rtl/070_navray_top.sv b/verilog/rtl/070_navray_top.sv
index 3f1cb17..fa8f8d2 100644
--- a/verilog/rtl/070_navray_top.sv
+++ b/verilog/rtl/070_navray_top.sv
@@ -1,7 +1,8 @@
-// Title: Top-level wrapper in SystemVerilog
+// Title: Top-level wrapper in SystemVerilog
+// File: navray_top.sv
// Author: Wallace Everest
-// Date: 23-NOV-2022
-// https://github.com/navray/tt02-square-root
+// Date: 23-NOV-2022
+// URL: https://github.com/navray/tt02-square-root
//
// Description:
// The square-root of an unsigned 7-bit input is displayed on a 7-segment output.
diff --git a/verilog/rtl/074_speed_test.v b/verilog/rtl/074_speed_test.v
index dbcbb34..8510d6b 100644
--- a/verilog/rtl/074_speed_test.v
+++ b/verilog/rtl/074_speed_test.v
@@ -57,7 +57,7 @@
module ring_osc(input nrst,output osc);
// We count for 1 scan_clk period which expected at 166uS (6KHz).
- // If the delay of one inverter is 20ps and the ring is 100 inverters long,
+ // If the delay of one inverter is 20ps and the ring is 150 inverters long,
// then the ring period is 6nS (2*150inv*20pS/inv)
// This is 166MHz so expect a count of 166*166 nominally.
// For more time resolution make scan_clk slower but that requires more
diff --git a/verilog/rtl/075_tt2.v b/verilog/rtl/075_tt2.v
index 57b9e52..5b7f3b4 100644
--- a/verilog/rtl/075_tt2.v
+++ b/verilog/rtl/075_tt2.v
@@ -31,7 +31,7 @@
wire pv_in_clk;
wire pv_in_cs;
- reg pv_in_cs_last;
+ reg [1:0] pv_in_cs_hist;
wire out_clk, out_cs, out_mosi;
assign io_out[0] = pv_in_clk;
@@ -49,7 +49,7 @@
wire [7:0] sp;
wire [7:0] kp;
wire [7:0] ki;
- wire [7:0] kd;
+ //wire [7:0] kd;
wire [15:0] stb_level;
//assign sp = cfg_buf[0][3:0];
@@ -62,60 +62,52 @@
assign sp = cfg_spi_buffer[7:0];
assign kp = cfg_spi_buffer[15:8];
assign ki = cfg_spi_buffer[23:16];
- assign kd = cfg_spi_buffer[31:24];
- assign stb_level = cfg_spi_buffer[47:32];
+ //assign kd = cfg_spi_buffer[31:24];
+ assign stb_level = cfg_spi_buffer[39:24];
wire pv_stb;
wire pid_stb;
reg pid_stb_d1;
+ wire pid_rst;
+ assign pid_rst = reset || !cfg_cs;
+
// I/O registers
reg [7:0] in_pv;
reg [7:0] out;
// Slave SPI for configuration
//wire cfg_spi_done;
- wire [47:0] cfg_spi_buffer;
- spi_slave_in #(.BITS(48)) cfg_spi(.reset(reset), .clk(clk), .cs(cfg_cs), .sck(cfg_clk), .mosi(cfg_mosi), .out_buf(cfg_spi_buffer));
+ wire [39:0] cfg_spi_buffer;
+ spi_slave_in #(.BITS(40)) cfg_spi(.reset(reset), .clk(clk), .cs(cfg_cs), .sck(cfg_clk), .mosi(cfg_mosi), .out_buf(cfg_spi_buffer));
// Shift input in
- spi_master_in spi_in(.reset(reset), .clk(clk),
+ spi_master_in spi_in(.reset(pid_rst), .clk(clk),
.miso(pv_in_miso), .start(pv_stb),
.out_buf(in_pv), .sck(pv_in_clk), .cs(pv_in_cs));
// Shift output out
- spi_master_out spi_out(.reset(reset), .clk(clk), .in_buf(out),
+ spi_master_out spi_out(.reset(pid_rst), .clk(clk), .in_buf(out),
.start(pid_stb_d1),
.sck(out_clk), .cs(out_cs), .mosi(out_mosi));
// PID core
- pid pid (.reset(reset), .clk(clk), .pv_stb(pid_stb),
+ pid pid (.reset(pid_rst), .clk(clk), .pv_stb(pid_stb),
.sp(sp), .pv(in_pv),
- .kp(kp), .ki(ki), .kd(kd),
+ .kp(kp), .ki(ki),
.stimulus(out));
strobe #(.BITS(16)) pv_stb_gen(.reset(reset), .clk(clk), .level(stb_level), .out(pv_stb));
- assign pid_stb = pv_in_cs && !pv_in_cs_last;
- //edge_detect pv_in_cs_pe(.reset(reset), .clk(clk), .sig(pv_in_cs), .pol(1'b1), .out(pid_stb));
+ assign pid_stb = pv_in_cs_hist[0] && !pv_in_cs_hist[1];
always @(posedge clk) begin
if (reset) begin
- //cfg_buf[0] <= 8'h4A;
- //cfg_buf[1] <= 8'h23;
- //cfg_buf[2] <= 8'h00;
- //cfg_buf[3] <= 8'h10;
pid_stb_d1 <= 'b0;
- pv_in_cs_last <= 'b0;
+ pv_in_cs_hist <= 'b0;
end else begin
- pv_in_cs_last <= pv_in_cs;
+ pv_in_cs_hist <= { pv_in_cs_hist[0], pv_in_cs };
pid_stb_d1 <= pid_stb;
- //if (cfg_spi_done) begin
- //cfg_buf[3] <= cfg_spi_buffer[7:0];
- //cfg_buf[2] <= cfg_spi_buffer[15:8];
- //cfg_buf[1] <= cfg_spi_buffer[23:16];
- //cfg_buf[0] <= cfg_spi_buffer[31:24];
- //end
end
end
diff --git a/verilog/rtl/084_cpu.v b/verilog/rtl/084_cpu.v
new file mode 100644
index 0000000..451fe33
--- /dev/null
+++ b/verilog/rtl/084_cpu.v
@@ -0,0 +1,369 @@
+
+//
+// (C) Copyright Paul Campbell 2022 taniwha@gmail.com
+// Released under an Apache License 2.0
+//
+
+`default_nettype none
+
+module moonbase_cpu_8bit #(parameter MAX_COUNT=1000) (input [7:0] io_in, output [7:0] io_out);
+
+ //
+ // External interface
+ //
+ // external address latch
+ // the external 12 bit address latch is loaded [5:0] from io_out[5:0] when io_out[7:6] is 10
+ // the external 12 bit address latch is loaded [11:6] from io_out[5:0] when io_out[7:6] is 11
+ // external SRAM (eg MWS5101AEL3) when io_out[7] is 0
+ // which nibble is from io_out[6]
+ // the external RAM always produces what is at the latch's addresses on io_in[5:2] when
+ // the external SRAM is written when io_out[7] is 0 and io_out[5] is 0
+ // io_out[6] can be used as an extra address bit to split the address space between
+ // code (1) and data (0) to use a 256-nibble sram (woot!)
+ // external devices when io_out[7] is 0:
+ // which nibble is from io_out[6]
+ // external devices can be read from io_in[7:6] (at address pointed to by the address latch)
+ // external devices can be written from io_out[3:0] (at address pointed to by the address latch)
+ // when io_out[4] is 0
+ //
+ // SRAM address space (data accesses):
+ // 0-0xfff external
+ // 0x1000-131 internal (internal ram cells, for filling up the die :-)
+ //
+
+ localparam N_LOCAL_RAM = 4;
+
+ wire clk = io_in[0];
+ wire reset = io_in[1];
+ wire [3:0]ram_in = io_in[5:2];
+ wire [1:0]data_in = io_in[7:6];
+
+ reg strobe_out; // address strobe - designed to be wired to a 7 bit latch and a MWS5101AEL3
+ reg nibble; // address/data nibble
+ reg write_data_n; // write enable for data
+ reg write_ram_n; // write enable for ram
+ reg addr_pc;
+ wire [11:0]data_addr = ((r_v[3]?r_y[11:0]:r_x[11:0])+{8'b000, r_v[2:0]});
+ wire is_local_ram = (r_v[3]?r_y[12]:r_x[12]);
+ wire write_local_ram = is_local_ram & !write_ram_n;
+ wire write_ext_ram_n = is_local_ram | write_ram_n;
+ wire [$clog2(N_LOCAL_RAM)-1:0]local_ram_addr = data_addr[$clog2(N_LOCAL_RAM)-1:0];
+ wire [11:0]addr_out = addr_pc ? r_pc : data_addr; // address out mux (PC or X/Y+off)
+ wire [5:0]addr_out_mux = (nibble?addr_out[11:6]:addr_out[5:0]); // mux-d by portion
+ assign io_out = {strobe_out, nibble, strobe_out? addr_out_mux : {write_ext_ram_n, write_data_n, !nibble?r_a[7:4]:r_a[3:0]}}; // mux address and data out
+
+ reg [11:0]r_pc, c_pc; // program counter // actual flops in the system
+ reg [12:0]r_x, c_x; // x index register // by convention r_* is a flop, c_* is the combinatorial that feeds it
+ reg [12:0]r_y, c_y; // y index register
+ reg [7:0]r_a, c_a; // accumulator
+ reg [7:0]r_b, c_b; // temp accumulator
+ reg r_c, c_c; // carry flag
+ reg [3:0]r_h, c_h; // operand temp (high)
+ reg [3:0]r_l, c_l; // operand temp (low)
+ reg [4:0]r_ee, c_ee; // extended const (bits 12:4)
+ reg [3:0]r_v, c_v; // operand temp (low)
+ reg [11:0]r_s0, c_s0; // call stack
+ reg [11:0]r_s1, c_s1;
+
+ //
+ // phase:
+ // 0 - instruction fetch addr
+ // 1 - instruction fetch dataL ins
+ // 2 - instruction fetch dataH V
+ // 4 - data/const fetch addr
+ // 5 - data/const fetch dataL tmp
+ // 6 - data/const fetch dataH tmp2
+ // 8 - execute/data store addr
+ // 9 - data store dataL (might not do this)
+ // a - data store dataH (might not do this)
+ //
+ reg [3:0]r_phase, c_phase; // CPU internal state machine
+
+ // instructions
+ //
+ // Registers: a,b 8 bit, x,y 13 bits, pc 12 bits
+ //
+ // 0v: add a, v(x/y) - sets C
+ // 1v: sub a, v(x/y) - sets C
+ // 2v: or a, v(x/y)
+ // 3v: and a, v(x/y)
+ // 4v: xor a, v(x/y)
+ // 5v: mov a, v(x/y)
+ // 6v: movd a, v(x/y)
+ // 70: add a, c
+ // 71: inc a
+ // 72: swap x, y
+ // 73: ret
+ // 74: add y, a
+ // 75: add x, a
+ // 76: inc y
+ // 77: inc x
+ // 78: mov a, y
+ // 79: mov a, x
+ // 7a: mov b, a
+ // 7b: swap b, a
+ // 7c: mov y, a
+ // 7d: mov x, a
+ // 7e: clr a
+ // 7f: mov a, pc
+ // 8v: nop
+ // 9v: nop
+ // av: movd v(x/y), a
+ // bv: mov v(x/y), a
+ // cv: nop
+ // dv: nop
+ // ev: nop
+ // f0 HL: mov a, #HL
+ // f1 HL: add a, #HL
+ // f2 HL: mov y, #EELL
+ // f3 HL: mov x, #EEHL
+ // f4 HL: jne a/c, EEHL if EE[4] then test c otherwise test a
+ // f5 HL: jeq a/c, EEHL if EE[4] then test c otherwise test a
+ // f6 HL: jmp/call EEHL if EE[4] call else jmp
+ // f7 HL: nop
+ //
+ // Memory access - addresses are 7 bits - v(X/y) is a 3-bit offset v[2:0]
+ // if v[3] it's Y+v[2:0]
+ // if !v[3] it's X+v[2:0]
+ //
+ // The general idea is that X normally points to a bank of in sram 8 'registers',
+ // a bit like an 8051's r0-7, while X is a more general index register
+ // (but you can use both if you need to do some copying)
+ //
+
+ reg [3:0]r_ins, c_ins; // fetched instruction
+
+ wire [8:0]c_add = {1'b0, r_a}+{1'b0, r_h, r_l}; // ALUs
+ wire [8:0]c_sub = {1'b0, r_a}-{1'b0, r_h, r_l};
+ wire [12:0]c_i_add = {r_v[0]?r_x[12]:r_y[12], (r_v[0]?r_x[11:0]:r_y[11:0])+(r_v[1]?12'b1:{4'b0,r_a})};
+ wire [11:0]c_pc_inc = r_pc+1;
+ wire [7:0]c_a_inc = r_a + {7'b0, r_c|r_v[0]};
+
+ reg [7:0]r_local_ram[0:N_LOCAL_RAM-1];
+
+ wire [7:0]local_ram = r_local_ram[local_ram_addr];
+ always @(posedge clk)
+ if (write_local_ram)
+ r_local_ram[local_ram_addr] <= r_a;
+
+ always @(*) begin
+ c_ins = r_ins;
+ c_x = r_x;
+ c_y = r_y;
+ c_a = r_a;
+ c_b = r_b;
+ c_s0 = r_s0;
+ c_s1 = r_s1;
+ c_l = r_l;
+ c_h = r_h;
+ c_ee = r_ee;
+ c_pc = r_pc;
+ c_c = r_c;
+ c_v = r_v;
+ write_data_n = 1;
+ write_ram_n = 1;
+ addr_pc = 'bx;
+ nibble = 'bx;
+ if (reset) begin // reset clears the state machine and sets PC to 0
+ c_y = 13'h1000; // point at internal sram
+ c_pc = 0;
+ c_phase = 0;
+ strobe_out = 1;
+ end else
+ case (r_phase) // synthesis full_case parallel_case
+ 0: begin // 0: address latch instruction PC
+ strobe_out = 1;
+ addr_pc = 1;
+ nibble = 0;
+ c_phase = 1;
+ end
+ 1: begin // 0: address latch instruction PC
+ strobe_out = 1;
+ addr_pc = 1;
+ nibble = 1;
+ c_phase = 2;
+ end
+ 2: begin // 1: read data in r_ins
+ strobe_out = 0;
+ c_ins = ram_in;
+ nibble = 0;
+ c_phase = 3;
+ end
+ 3: begin // 3: read data in r_v
+ strobe_out = 0;
+ c_v = ram_in;
+ nibble = 1;
+ c_pc = c_pc_inc;
+ case (r_ins) // synthesis full_case parallel_case
+ 7, 8, 9, 10, 11, 12, 13, 14: c_phase = 12;// some instructions don't have a 2nd fetch
+ default: c_phase = 4;
+ endcase
+ end
+ 4: begin // 4 address latch for next operand
+ strobe_out = 1;
+ addr_pc = r_ins[3:2] == 3; // some instructions read a 2nd operand, the rest the come here read a memory location
+ nibble = 0;
+ c_phase = r_ins[3:2] != 3 && is_local_ram ? 7 : 5;
+ end
+ 5: begin // 4 address latch for next operand
+ strobe_out = 1;
+ addr_pc = r_ins[3:2] == 3; // some instructions read a 2nd operand, the rest the come here read a memory location
+ nibble = 1;
+ c_phase = 6;
+ end
+ 6: begin // 5 read next operand r_hi
+ strobe_out = 0;
+ nibble = 0;
+ c_h = ((r_ins[3:1] == 3)? 4'b0 : ram_in);
+ c_phase = 7;
+ end
+ 7: begin // 5 read next operand r_lo
+ strobe_out = 0;
+ nibble = 1;
+ if (is_local_ram&&r_ins != 4'hf) begin
+ c_h = local_ram[7:4];
+ c_l = local_ram[3:0];
+ end else begin
+ c_l = ((r_ins[3:1] == 3)?{2'b0,data_in}:ram_in); // read the actial data, movd comes from upper bits
+ end
+ if (r_ins == 4'hf) // if we fetched from PC increment it
+ c_pc = c_pc_inc;
+ c_phase = (r_ins == 4'hf && r_v[3:1] != 0) ? 8: 12;
+ end
+ 8: begin // 4 address latch for next operand
+ strobe_out = 1;
+ addr_pc = 1;
+ nibble = 0;
+ c_phase = 9;
+ end
+ 9: begin // 4 address latch for next operand
+ strobe_out = 1;
+ addr_pc = 1;
+ nibble = 1;
+ c_phase = 10;
+ end
+ 10: begin // 5 read next operand r_hi
+ strobe_out = 0;
+ nibble = 0;
+ c_ee[4] = ram_in[0];
+ c_phase = 11;
+ end
+ 11: begin // 5 read next operand r_lo
+ strobe_out = 0;
+ nibble = 1;
+ c_ee[3:0] = ram_in;
+ c_pc = c_pc_inc;
+ c_phase = 12;
+ end
+ 12: begin // 6 execute stage
+ strobe_out = r_ins[3:1] == 5; // if writing to anything latch address
+ addr_pc = 0;
+ c_phase = 0; // if not writing go back
+ nibble = 0;
+ case (r_ins)// synthesis full_case parallel_case
+ 0: begin c_c = c_add[8]; c_a = c_add[7:0]; end // add a, v(x)
+ 1: begin c_c = c_sub[8]; c_a = c_sub[7:0]; end // sub a, v(x)
+ 2: c_a = r_a|{r_h, r_l}; // or a, v(x)
+ 3: c_a = r_a&{r_h, r_l}; // sub a, v(x)
+ 4: c_a = r_a^{r_h, r_l}; // xor a, v(x)
+ 5, // mov a, v(x)
+ 6: c_a = {r_h, r_l}; // movd a, v(x)
+ 7: case (r_v) // synthesis full_case parallel_case
+ 0: c_a = c_a_inc; // 0 add a, c
+ 1: c_a = c_a_inc; // 1 inc a
+ 2: begin c_x = r_y; c_y = r_x; end // 2 swap y, x
+ 3: begin // 3 ret
+ c_pc = r_s0;
+ c_s0 = r_s1;
+ end
+ 4: c_y = c_i_add; // 4 add y, a
+ 5: c_x = c_i_add; // 5 add x, a
+ 6: c_y = c_i_add; // 6 add y, #1
+ 7: c_x = c_i_add; // 7 add y, #1
+ 8: c_a = r_y[7:0]; // 8 mov a, y
+ 9: c_a = r_x[7:0]; // 9 mov a, x
+ 10: c_b = r_a; // a mov b, a
+ 11: begin c_b = r_a; c_a = r_b; end // b swap b, a
+ 12: c_y[7:0] = r_a; // c mov y, a
+ 13: c_x[7:0] = r_a; // d mov x, a
+ 14: c_a = 0; // e clr a
+ 15: c_a = r_pc; // f mov a, pc
+ default: ;
+ endcase
+ 8: ; // noop
+ 9: ; // noop
+ 10, // movd v(x), a
+ 11: c_phase = is_local_ram ? 15:13; // mov v(x), a
+ 12: ; // noop
+ 13: ; // noop
+ 14: ; // noop
+
+ 15: case (r_v) // synthesis full_case parallel_case
+ 0: c_a = {r_h, r_l}; // mov a, #HL
+ 1: begin c_c = c_add[8]; c_a = c_add[7:0]; end // add a, #HL
+ 2: c_y = {r_ee, r_h, r_l}; // mov y, #VV
+ 3: c_x = {r_ee, r_h, r_l}; // mov x, #VV
+ 4: c_pc = (r_ee[4]?!r_c : r_a != 0) ? {r_ee[3:0], r_h, r_l} : r_pc; // jne a/c, VV
+ 5: c_pc = (r_ee[4]? r_c : r_a == 0) ? {r_ee[3:0], r_h, r_l} : r_pc; // jeq a/c, VV
+ 6: begin c_pc = {r_ee[3:0], r_h, r_l}; // jmp VV
+ if (r_ee[4]) begin // call
+ c_s0 = r_pc;
+ c_s1 = r_s0;
+ end
+ end
+ default: ;
+ endcase
+ endcase
+ end
+ 13: begin
+ strobe_out = 1;
+ addr_pc = 0;
+ nibble = 1;
+ c_phase = 14;
+ end
+ 14: begin // 7 write data stage - assert appropriate write strobe
+ strobe_out = 0;
+ write_data_n = r_ins[0];
+ write_ram_n = ~r_ins[0];
+ nibble = 0;
+ c_phase = 15;
+ end
+ 15: begin // 7 write data stage - assert appropriate write strobe
+ strobe_out = 0;
+ nibble = 1;
+ write_data_n = r_ins[0];
+ write_ram_n = ~r_ins[0];
+ c_phase = 0;
+ end
+ endcase
+ end
+
+ always @(posedge clk) begin
+ r_a <= c_a;
+ r_b <= c_b;
+ r_c <= c_c;
+ r_x <= c_x;
+ r_y <= c_y;
+ r_ins <= c_ins;
+ r_v <= c_v;
+ r_l <= c_l;
+ r_h <= c_h;
+ r_ee <= c_ee;
+ r_pc <= c_pc;
+ r_phase <= c_phase;
+ r_s0 <= c_s0;
+ r_s1 <= c_s1;
+ end
+
+endmodule
+
+/* For Emacs:
+ * Local Variables:
+ * mode:c
+ * indent-tabs-mode:t
+ * tab-width:4
+ * c-basic-offset:4
+ * End:
+ * For VIM:
+ * vim:set softtabstop=4 shiftwidth=4 tabstop=4:
+ */
diff --git a/verilog/rtl/087_freq_counter.v b/verilog/rtl/087_freq_counter.v
new file mode 100644
index 0000000..3cd5fdf
--- /dev/null
+++ b/verilog/rtl/087_freq_counter.v
@@ -0,0 +1,73 @@
+`default_nettype none
+
+module aramsey118_freq_counter #(
+ parameter DEPTH = 200
+) (
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+ // Precalculate the boundaries
+ localparam integer freq_0 = $ceil(DEPTH * 0.0); // not used, here for completeness
+ localparam integer freq_1 = $ceil(DEPTH * 0.1);
+ localparam integer freq_2 = $ceil(DEPTH * 0.2);
+ localparam integer freq_3 = $ceil(DEPTH * 0.3);
+ localparam integer freq_4 = $ceil(DEPTH * 0.4);
+ localparam integer freq_5 = $ceil(DEPTH * 0.5);
+ localparam integer freq_6 = $ceil(DEPTH * 0.6);
+ localparam integer freq_7 = $ceil(DEPTH * 0.7);
+ localparam integer freq_8 = $ceil(DEPTH * 0.8);
+ localparam integer freq_9 = $ceil(DEPTH * 0.9);
+
+ wire clk = io_in[0];
+ wire reset = io_in[1];
+ wire sig = io_in[2];
+ wire [6:0] led_out;
+ assign io_out[6:0] = led_out;
+ assign io_out[7] = sig;
+
+ wire [$clog2(DEPTH)-1:0] avg;
+ reg sig_d1;
+ reg diff;
+ reg [3:0] digit;
+
+
+ always @(posedge clk) begin
+ // if reset, set counter to 0
+ if (reset) begin
+ sig_d1 <= 0;
+ diff <= 0;
+ digit <= 0;
+ end else begin
+ sig_d1 <= sig;
+ diff <= (sig ^ sig_d1);
+ if ((avg <= $unsigned(freq_1))) begin
+ digit <= 0;
+ end else if ((avg > $unsigned(freq_1)) && (avg <= $unsigned(freq_2))) begin
+ digit <= 1;
+ end else if ((avg > $unsigned(freq_2)) && (avg <= $unsigned(freq_3))) begin
+ digit <= 2;
+ end else if ((avg > $unsigned(freq_3)) && (avg <= $unsigned(freq_4))) begin
+ digit <= 3;
+ end else if ((avg > $unsigned(freq_4)) && (avg <= $unsigned(freq_5))) begin
+ digit <= 4;
+ end else if ((avg > $unsigned(freq_5)) && (avg <= $unsigned(freq_6))) begin
+ digit <= 5;
+ end else if ((avg > $unsigned(freq_6)) && (avg <= $unsigned(freq_7))) begin
+ digit <= 6;
+ end else if ((avg > $unsigned(freq_7)) && (avg <= $unsigned(freq_8))) begin
+ digit <= 7;
+ end else if ((avg > $unsigned(freq_8)) && (avg <= $unsigned(freq_9))) begin
+ digit <= 8;
+ end else begin
+ digit <= 9;
+ end
+ end
+ end
+
+ // instantiate segment display
+ seg7 seg7(.counter(digit), .segments(led_out));
+
+ // instantiate moving average
+ moving_avg #(.DEPTH(DEPTH)) moving_avg(.data_i(diff), .reset, .clk, .avg_o(avg));
+endmodule
diff --git a/verilog/rtl/088_thunderbird_taillight_ctrl.v b/verilog/rtl/088_thunderbird_taillight_ctrl.v
new file mode 100644
index 0000000..d632a83
--- /dev/null
+++ b/verilog/rtl/088_thunderbird_taillight_ctrl.v
@@ -0,0 +1,108 @@
+`default_nettype none `timescale 1ns / 1ps
+// coded by Hirosh Dabui 2012
+// based on T-Bird tail-lights machine from digital design book
+// table 9-20 in VHDL
+/* verilator lint_off MULTITOP */
+module thunderbird_taillight_ctrl #(
+ parameter MAX_COUNT = 1000,
+ parameter SYSTEM_FREQ = 6250,
+ parameter HZ = 8
+) (
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+ wire clk = io_in[0];
+ wire reset = io_in[1];
+ wire left = io_in[2];
+ wire right = io_in[3];
+ wire haz = io_in[4];
+
+ wire [5:0] lights = state;
+ assign io_out[7:0] = {2'b00, lights};
+
+ wire div;
+ divider #(
+ .SYSTEM_FREQ(SYSTEM_FREQ),
+ .HZ (HZ)
+ ) divider_i (
+ .clk (clk),
+ .reset (reset),
+ .divider(div)
+ );
+
+ localparam IDLE = 6'b000_000;
+ localparam L3 = 6'b111_000;
+ localparam L2 = 6'b011_000;
+ localparam L1 = 6'b001_000;
+ localparam R3 = 6'b000_111;
+ localparam R2 = 6'b000_110;
+ localparam R1 = 6'b000_100;
+ localparam LR3 = 6'b111_111;
+
+ reg [5:0] state, next_state;
+
+ always @(posedge clk) begin
+ if (reset) begin
+ state <= IDLE;
+ end else begin
+ if (div) begin
+ state <= next_state;
+ end
+ end
+ end
+
+ always @(*) begin
+ next_state = state;
+
+ case (state)
+ IDLE: begin
+ case (1'b1)
+ haz | (left & right): next_state = LR3;
+ left: next_state = L1;
+ right: next_state = R1;
+ default: next_state = IDLE;
+ endcase
+ end
+
+ L1: next_state = haz ? LR3 : L2;
+ L2: next_state = haz ? LR3 : L3;
+ L3: next_state = haz ? LR3 : IDLE;
+
+ R1: next_state = haz ? LR3 : R2;
+ R2: next_state = haz ? LR3 : R3;
+ R3: next_state = haz ? LR3 : IDLE;
+
+ LR3: next_state = IDLE;
+
+ default: next_state = state;
+ endcase
+ end
+
+endmodule
+
+module divider #(
+ parameter SYSTEM_FREQ = 6250,
+ parameter HZ = 8
+) (
+ input clk,
+ input reset,
+ output divider
+);
+ localparam CYCLES = SYSTEM_FREQ / HZ;
+ reg [$clog2(CYCLES) -1:0] cnt;
+ always @(posedge clk) begin
+ if (reset) begin
+ cnt <= 0;
+ end else begin
+ cnt <= cnt + 1;
+ /* verilator lint_off WIDTH */
+ if (cnt >= (CYCLES - 1)) begin
+ cnt <= 0;
+ end
+ /* verilator lint_on WIDTH */
+ end
+ end
+ assign divider = cnt == 0;
+endmodule
+/* verilator lint_on MULTITOP */
diff --git a/verilog/rtl/089_fpga.v b/verilog/rtl/089_fpga.v
new file mode 100644
index 0000000..2fb7e91
--- /dev/null
+++ b/verilog/rtl/089_fpga.v
@@ -0,0 +1,180 @@
+`default_nettype none
+`default_nettype none
+
+// Top level io for this module should stay the same to fit into the scan_wrapper.
+// The pin connections within the user_module are up to you,
+// although (if one is present) it is recommended to place a clock on io_in[0].
+// This allows use of the internal clock divider if you wish.
+module gatecat_fpga_top(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+ wire cfg_mode, cfg_frameinc, cfg_framestrb, cfg_dataclk;
+ wire [3:0] cfg_sel;
+
+ sky130_fd_sc_hd__clkbuf_2 mode_clkbuf(.A(io_in[3]), .X(cfg_mode));
+ sky130_fd_sc_hd__clkbuf_2 frameinc_clkbuf(.A(io_in[1]), .X(cfg_frameinc));
+ sky130_fd_sc_hd__clkbuf_2 framestrb_clkbuf(.A(io_in[2]), .X(cfg_framestrb));
+ assign cfg_dataclk = io_in[0];
+
+ wire cfg_datain;
+ sky130_fd_sc_hd__buf_2 din_buf (.A(io_in[4]), .X(cfg_datain));
+
+ localparam W = 5;
+ localparam H = 6;
+ localparam FW = W * 4;
+ localparam FH = H * 2;
+
+ reg [$clog2(FH)-1:0] frame_ctr;
+ reg [FW-1:0] frame_sr;
+
+ always @(posedge cfg_frameinc, negedge cfg_mode)
+ if (~cfg_mode)
+ frame_ctr <= 0;
+ else
+ frame_ctr <= frame_ctr + 1'b1;
+
+ // avoid a shift register for the frame data because that's the highest hold risk
+ always @(posedge cfg_dataclk)
+ frame_sr <= {cfg_datain, frame_sr[FW-1:1]};
+
+ wire [FH-1:0] frame_strb;
+ wire gated_strobe = cfg_mode & cfg_framestrb;
+ generate;
+ genvar ii;
+ for (ii = 0; ii < FH; ii = ii + 1'b1) begin
+ //make sure this is glitch free
+ sky130_fd_sc_hd__nand2_2 cfg_nand (.A(gated_strobe), .B(frame_ctr == ii), .Y(frame_strb[ii]));
+ end
+ endgenerate
+
+ wire fab_clk = io_in[0];
+ wire [6:0] fab_din;
+ sky130_fd_sc_hd__buf_1 din_buf[6:0] (.A(io_in[7:1]), .X(fab_din));
+
+ wire [0:W-1] cell_q[0:H-1];
+ generate
+ genvar xx;
+ genvar yy;
+ for (yy = 0; yy < H; yy = yy + 1'b1) begin: y_c
+ for (xx = 0; xx < W; xx = xx + 1'b1) begin: x_c
+ wire ti, bi, li, ri;
+ if (yy > 0) assign ti = cell_q[yy-1][xx]; else assign ti = fab_din[xx];
+ if (yy < H-1) assign bi = cell_q[yy+1][xx]; else assign bi = cell_q[yy][xx];
+ if (xx > 0) assign li = cell_q[yy][xx-1]; else assign li = fab_din[yy + 1];
+ if (xx < W-1) assign ri = cell_q[yy][xx+1]; else assign ri = cell_q[yy][xx];
+ gatecat_logic_cell #(.has_ff(1'b1)) lc_i (
+ .CLK(fab_clk),
+ .cfg_mode(cfg_mode),
+ .cfg_strb(frame_strb[yy * 2 +: 2]),
+ .cfg_data(frame_sr[xx * 4 +: 4]),
+ .T(ti), .B(bi), .L(li),. R(ri),
+ .Q(cell_q[yy][xx])
+ );
+ end
+ end
+ endgenerate
+
+ assign io_out = {cell_q[5][W-1], cell_q[4][W-1], cell_q[3][W-1], cell_q[H-1]};
+
+
+endmodule
+
+module gatecat_logic_cell (
+ input CLK,
+ input cfg_mode,
+ input [1:0] cfg_strb,
+ input [3:0] cfg_data,
+ input T, L, R, B,
+ output Q
+);
+ parameter has_ff = 1'b0;
+ // config storage
+ wire [7:0] cfg;
+ generate
+ genvar ii, jj;
+ for (ii = 0; ii < 2; ii = ii + 1'b1)
+ for (jj = 0; jj < 4; jj = jj + 1'b1)
+ sky130_fd_sc_hd__dlxtn_1 cfg_lat_i (
+ .D(cfg_data[jj]),
+ .GATE_N(cfg_strb[ii]),
+ .Q(cfg[ii*4 + jj])
+ );
+ endgenerate
+
+ wire i0, i1;
+ // I input muxes
+ wire i0a, i0b;
+ sky130_fd_sc_hd__nand2_1 i0muxa0 (
+ .A(T), .B(cfg[0]),
+ .Y(i0a)
+ );
+ sky130_fd_sc_hd__mux2i_1 i0muxa1 (
+ .A0(R), .A1(L), .S(cfg[0]),
+ .Y(i0b)
+ );
+
+ sky130_fd_sc_hd__mux2i_1 i0muxb (
+ .A0(i0a), .A1(i0b), .S(cfg[1]),
+ .Y(i0)
+ );
+
+ wire i1a, i1b;
+ sky130_fd_sc_hd__and2_1 i1muxa0 (
+ .A(cfg[2]), .B(L),
+ .X(i1a)
+ );
+ sky130_fd_sc_hd__mux2i_1 i1muxa1 (
+ .A0(B), .A1(R), .S(cfg[2]),
+ .Y(i1b)
+ );
+ sky130_fd_sc_hd__mux2i_1 i1muxb (
+ .A0(i1a), .A1(i1b), .S(cfg[3]),
+ .Y(i1)
+ );
+ // S input mux
+ wire s0s, s0, s0a, s0b;
+
+ sky130_fd_sc_hd__nand2_1 s0muxa0 (
+ .A(T), .B(cfg[4]),
+ .Y(s0a)
+ );
+ sky130_fd_sc_hd__mux2i_1 s0muxa1 (
+ .A0(R), .A1(L), .S(cfg[4]),
+ .Y(s0b)
+ );
+
+ sky130_fd_sc_hd__mux2i_1 s0muxb (
+ .A0(s0a), .A1(s0b), .S(cfg[5]),
+ .Y(s0s)
+ );
+ // S invert
+ sky130_fd_sc_hd__xnor2_1 sinv (
+ .A(s0s), .B(cfg[6]), .Y(s0)
+ );
+ // The logic element
+ wire muxo_n;
+ sky130_fd_sc_hd__mux2i_1 lmux (
+ .A0(i0), .A1(i1), .S(s0), .Y(muxo_n)
+ );
+ // The DFF
+ generate if (has_ff) begin: dff
+ wire dffo_n;
+ sky130_fd_sc_hd__dfsbp_1 dff(
+ .D(muxo_n),
+ .SET_B(~cfg_mode),
+ .CLK(CLK),
+ .Q(dffo_n)
+ );
+ // The final output mux
+ sky130_fd_sc_hd__mux2i_1 ffsel (
+ .A0(muxo_n), .A1(dffo_n), .S(cfg[7]), .Y(Q)
+ );
+ end else begin
+ sky130_fd_sc_hd__inv_1 linv (
+ .A(muxo_n), .Y(Q)
+ );
+ end
+ endgenerate
+endmodule
diff --git a/verilog/rtl/092_whisk.v b/verilog/rtl/092_whisk.v
new file mode 100644
index 0000000..9a40d0b
--- /dev/null
+++ b/verilog/rtl/092_whisk.v
@@ -0,0 +1,1181 @@
+// ============================================================================
+// Whisk: a 16-bit bit-serial RISC processor (c) Luke Wren 2022
+// SPDX-License-Identifier: Apache-2.0
+// ============================================================================
+
+// Whisk is a 16-bit bit-serial processor, with external SPI SRAM interface,
+// designed in a hurry for Tiny Tapeout 2. See README.md for an overview of
+// the instruction set. Supporting hardware:
+//
+// - SPI SRAM with sequential mode and 16-bit addressing, e.g. Microchip
+// 23K256T-I (32 kiB SRAM)
+//
+// - One 8-bit parallel-to-serial shift register, for input port
+//
+// - Two 8-bit serial-to-parallel shift registers, for output port
+//
+// - A host device capable of loading the SPI SRAM, setting it to sequential
+// mode, and releasing Whisk's reset. I'll probably use a Pico.
+//
+// There will be a board with all of these components ready for bringup, and
+// it will be added to this repository (also I will probably make a few of
+// them, and will gladly send you one if you ask). However this will not be
+// done before tapeout, as I started this project a week before the
+// deadline!
+
+`ifdef WHISK_DEFAULT_NETTYPE_NONE
+`default_nettype none
+`endif
+
+`ifndef WHISK_NO_CELLS
+`define WHISK_CELLS_SKY130
+`endif
+
+// ============================================================================
+// Module wren6991_whisk_tt2_io_wrapper: Top level for TT2 synthesis.
+// instantiate whisk_top, and map named ports to numbered TT2 inputs/outputs
+// ============================================================================
+
+module wren6991_whisk_tt2_io_wrapper (
+ input wire [7:0] io_in,
+ output wire [7:0] io_out
+);
+
+// Global signals
+wire io_clk = io_in[0];
+wire io_rst_n = io_in[1];
+
+// SPI memory interface
+wire io_mem_sdi = io_in[2];
+
+wire io_mem_csn;
+wire io_mem_sck;
+wire io_mem_sdo;
+
+assign io_out[0] = io_mem_csn;
+assign io_out[1] = io_mem_sck;
+assign io_out[2] = io_mem_sdo;
+
+// IO port (shift register interface)
+wire io_ioport_sdi = io_in[3];
+
+wire io_ioport_sck;
+wire io_ioport_sdo;
+wire io_ioport_latch_i;
+wire io_ioport_latch_o;
+
+assign io_out[3] = io_ioport_sck;
+assign io_out[4] = io_ioport_sdo;
+assign io_out[5] = io_ioport_latch_i;
+assign io_out[6] = io_ioport_latch_o;
+
+// Be a good neighbour
+assign io_out[7] = 1'b0;
+
+whisk_top top_u (
+ .io_clk (io_clk),
+ .io_rst_n (io_rst_n),
+
+ .io_mem_sdi (io_mem_sdi),
+ .io_mem_csn (io_mem_csn),
+ .io_mem_sck (io_mem_sck),
+ .io_mem_sdo (io_mem_sdo),
+
+ .io_ioport_sdi (io_ioport_sdi),
+ .io_ioport_sck (io_ioport_sck),
+ .io_ioport_sdo (io_ioport_sdo),
+ .io_ioport_latch_i (io_ioport_latch_i),
+ .io_ioport_latch_o (io_ioport_latch_o)
+);
+
+endmodule
+
+// ============================================================================
+// Module whisk_top: instantiate the CPU core together with the SPI mem
+// serdes and IO port serdes.
+// ============================================================================
+
+module whisk_top (
+ input wire io_clk,
+ input wire io_rst_n,
+
+ input wire io_mem_sdi,
+ output wire io_mem_csn,
+ output wire io_mem_sck,
+ output wire io_mem_sdo,
+
+ input wire io_ioport_sdi,
+ output wire io_ioport_sck,
+ output wire io_ioport_sdo,
+ output wire io_ioport_latch_i,
+ output wire io_ioport_latch_o
+);
+
+// ----------------------------------------------------------------------------
+// Clock/reset wrangling
+
+// Don't buffer the clock -- seems like the scripts define a clock on io_in[0]?
+wire clk = io_clk;
+
+// Synchronise reset removal to clk
+reg [1:0] reset_sync;
+wire rst_n = reset_sync[1];
+
+always @ (posedge clk or negedge io_rst_n) begin
+ if (!io_rst_n) begin
+ reset_sync <= 2'd00;
+ end else begin
+ reset_sync <= ~(~reset_sync << 1);
+ end
+end
+
+// ----------------------------------------------------------------------------
+// Processor instantiation
+
+wire mem_sck_en_next;
+wire mem_sdo_next;
+wire mem_csn_next;
+wire mem_sdi_prev;
+
+wire ioport_sck_en_next;
+wire ioport_sdo_next;
+wire ioport_sdi_prev;
+wire ioport_latch_i_next;
+wire ioport_latch_o_next;
+
+whisk_cpu cpu (
+ .clk (clk),
+ .rst_n (rst_n),
+
+ .mem_sck_en_next (mem_sck_en_next),
+ .mem_sdo_next (mem_sdo_next),
+ .mem_csn_next (mem_csn_next),
+ .mem_sdi_prev (mem_sdi_prev),
+
+ .ioport_sck_en_next (ioport_sck_en_next),
+ .ioport_sdo_next (ioport_sdo_next),
+ .ioport_sdi_prev (ioport_sdi_prev),
+ .ioport_latch_i_next (ioport_latch_i_next),
+ .ioport_latch_o_next (ioport_latch_o_next)
+);
+
+// ----------------------------------------------------------------------------
+// Serdes (IO registers)
+
+whisk_spi_serdes mem_serdes_u (
+ .clk (clk),
+ .rst_n (rst_n),
+
+ .sdo (mem_sdo_next),
+ .sck_en (mem_sck_en_next),
+ .csn (mem_csn_next),
+ .sdi (mem_sdi_prev),
+
+ .padout_sck (io_mem_sck),
+ .padout_csn (io_mem_csn),
+ .padout_sdo (io_mem_sdo),
+ .padin_sdi (io_mem_sdi)
+);
+
+whisk_ioport_serdes io_serdes_u (
+ .clk (clk),
+ .rst_n (rst_n),
+
+ .sdo (ioport_sdo_next),
+ .sck_en (ioport_sck_en_next),
+ .latch_i (ioport_latch_i_next),
+ .latch_o (ioport_latch_o_next),
+ .sdi (ioport_sdi_prev),
+
+ .padout_sdo (io_ioport_sdo),
+ .padout_sck (io_ioport_sck),
+ .padout_latch_i (io_ioport_latch_i),
+ .padout_latch_o (io_ioport_latch_o),
+ .padin_sdi (io_ioport_sdi)
+);
+
+endmodule
+
+// ============================================================================
+// Module whisk_cpu: top-level for the Whisk processor, minus the IO wrapper
+// and the SPI/IOPORT serdes
+// ============================================================================
+
+module whisk_cpu (
+ input wire clk,
+ input wire rst_n,
+
+ // SPI SRAM interface
+ output wire mem_sck_en_next,
+ output wire mem_sdo_next,
+ output wire mem_csn_next,
+ input wire mem_sdi_prev,
+
+ // Shift registers for IO port
+ output wire ioport_sck_en_next,
+ output wire ioport_sdo_next,
+ input wire ioport_sdi_prev,
+ output wire ioport_latch_i_next,
+ output wire ioport_latch_o_next
+);
+
+// ----------------------------------------------------------------------------
+// Constants
+
+// Machine size
+localparam W_INSTR = 16;
+localparam W_DATA = 16;
+localparam N_REGS = 6;
+
+// Instruction layout
+localparam INSTR_OP_LSB = 0;
+localparam INSTR_OP_MSB = 3;
+localparam INSTR_COND_LSB = 4;
+localparam INSTR_COND_MSB = 6;
+localparam INSTR_RT_LSB = 7;
+localparam INSTR_RT_MSB = 9;
+localparam INSTR_RS_LSB = 10;
+localparam INSTR_RS_MSB = 12;
+localparam INSTR_RD_LSB = 13;
+localparam INSTR_RD_MSB = 15;
+
+// Major opcodes (instr[3:0])
+localparam [3:0] OP_ADD = 4'h0; // rd = rs + rt
+localparam [3:0] OP_SUB = 4'h1; // rd = rs - rt
+localparam [3:0] OP_AND = 4'h2; // rd = rs & rt
+localparam [3:0] OP_ANDN = 4'h3; // rd = rs & ~rt
+localparam [3:0] OP_OR = 4'h4; // rd = rs | rt
+localparam [3:0] OP_SHIFT = 4'h5; // Minor opcode in rt
+localparam [3:0] OP_INOUT = 4'h6; // Minor opcode in rs
+
+localparam [3:0] OP_LDR = 4'h8; // rd = mem[rs];
+localparam [3:0] OP_LDR_IB = 4'h9; // rs += rt; rd = mem[rs];
+localparam [3:0] OP_LDR_DA = 4'ha; // rd = mem[rs]; rs -= rt
+localparam [3:0] OP_LDR_IB_DA = 4'hb; // rs += rt; rd = mem[rs]; rs -= rt
+
+localparam [3:0] OP_STR = 4'hc; // mem[rs] = rd;
+localparam [3:0] OP_STR_IB = 4'hd; // rs += rt; mem[rs] = rd;
+localparam [3:0] OP_STR_DA = 4'he; // mem[rs] = rd; rs -= rt
+localparam [3:0] OP_STR_IB_DA = 4'hf; // rs += rt; mem[rs] = rd; rs -= rt
+
+// Minor opcodes (rt)
+localparam [2:0] OP2_SRL = 3'h0;
+localparam [2:0] OP2_SRA = 3'h1;
+localparam [2:0] OP2_SLL = 3'h4;
+
+// Minor opcodes (rs)
+localparam [2:0] OP2_IN = 3'h0;
+localparam [2:0] OP2_OUT = 3'h4;
+
+// ----------------------------------------------------------------------------
+// Main control state machine
+
+wire [W_INSTR-1:0] instr;
+
+wire [INSTR_OP_MSB -INSTR_OP_LSB :0] instr_op;
+wire [INSTR_COND_MSB-INSTR_COND_LSB:0] instr_cond;
+wire [INSTR_RT_MSB -INSTR_RT_LSB :0] instr_rt;
+wire [INSTR_RS_MSB -INSTR_RS_LSB :0] instr_rs;
+wire [INSTR_RD_MSB -INSTR_RD_LSB :0] instr_rd;
+
+assign {instr_rd, instr_rs, instr_rt, instr_cond, instr_op} = instr;
+
+wire instr_op_ls = instr_op[3]; // Whether an instruction is a load/store
+wire instr_op_st_nld = instr_op[2]; // Whether a load/store is a load or store
+wire instr_op_ls_da = instr_op[1]; // Whether a load/store has decrement-after
+wire instr_op_ls_ib = instr_op[0]; // Whether a load/store has increment-before
+
+reg [3:0] bit_ctr;
+reg [2:0] state;
+reg instr_cond_true;
+reg instr_has_imm_operand;
+
+// Note there is a 2 cycle delay from issuing a bit on SDO to getting a bit
+// back on SDI. This is handled with a 2-cycle stall after issuing a read
+// address, so that e.g. S_FETCH always has the first instruction bit
+// available on the first cycle.
+
+localparam [2:0] S_FETCH = 3'd0; // Sample 16 instr bits, increment PC
+localparam [2:0] S_EXEC = 3'd1; // Loop all GPRs, write one GPR
+localparam [2:0] S_PC_NONSEQ0 = 3'd2; // Issue cmd, then issue 2 PC bits
+localparam [2:0] S_PC_NONSEQ1 = 3'd3; // Issue rest of PC bits, stall 2 cycles
+localparam [2:0] S_LS_ADDR0 = 3'd4; // Issue cmd; if load, issue 2 addr bits
+localparam [2:0] S_LS_ADDR1 = 3'd5; // Issue addr; if load, stall 2 cycles
+localparam [2:0] S_LS_DATA = 3'd6; // Issue store data, or sample load data
+localparam [2:0] S_LS_IMMPD = 3'd7; // Re-read imm for imm post-decrement
+
+reg [3:0] bit_ctr_nxt_wrap;
+reg [3:0] bit_ctr_nxt;
+reg [2:0] state_nxt_wrap;
+reg [2:0] state_nxt;
+
+always @ (*) begin
+ state_nxt_wrap = state;
+ bit_ctr_nxt_wrap = bit_ctr + 4'h1;
+ case (state)
+ S_FETCH: begin
+ if (!instr_cond_true) begin
+ if (instr_has_imm_operand) begin
+ // Need to dump 16 more bits, and if we stay in this
+ // state then instr_cond_true will lose its value, so take a detour
+ state_nxt_wrap = S_LS_IMMPD;
+ end else begin
+ state_nxt_wrap = S_FETCH;
+ end
+ end else if (instr[4] && !instr[1]) begin
+ // Load/store with no preincrement, go straight to address
+ // state (note instruction is left-shifted by 1 at this point)
+ state_nxt_wrap = S_LS_ADDR0;
+ bit_ctr_nxt_wrap = instr[3] ? 4'h8 : 4'h6; // FIXME no chip select deassert on store!
+ end else begin
+ state_nxt_wrap = S_EXEC;
+ end
+ end
+ S_EXEC: begin
+ if (instr_op_ls) begin
+ state_nxt_wrap = S_LS_ADDR0;
+ bit_ctr_nxt_wrap = instr[3] ? 4'h8 : 4'h6;
+ end else if (instr_rd == 3'd7) begin
+ state_nxt_wrap = S_PC_NONSEQ0;
+ bit_ctr_nxt_wrap = 4'h6;
+ end else begin
+ state_nxt_wrap = S_FETCH;
+ end
+ end
+ S_PC_NONSEQ0: begin
+ state_nxt_wrap = S_PC_NONSEQ1;
+ end
+ S_PC_NONSEQ1: begin
+ if (!instr_cond_true) begin
+ // Have just been reset, instr is invalid
+ state_nxt_wrap = S_FETCH;
+ end else if (instr_has_imm_operand && instr_op_ls && instr_op_ls_da) begin
+ state_nxt_wrap = S_LS_IMMPD;
+ end else begin
+ state_nxt_wrap = S_FETCH;
+ end
+ end
+ S_LS_ADDR0: begin
+ state_nxt_wrap = S_LS_ADDR1;
+ end
+ S_LS_ADDR1: begin
+ state_nxt_wrap = S_LS_DATA;
+ end
+ S_LS_DATA: begin
+ state_nxt_wrap = S_PC_NONSEQ0;
+ bit_ctr_nxt_wrap = 4'h6;
+ end
+ S_LS_IMMPD: begin
+ if (instr_cond_true) begin
+ state_nxt_wrap = S_PC_NONSEQ0;
+ bit_ctr_nxt_wrap = 4'h6;
+ end else begin
+ // Borrowed to dump the second half of a false-predicate instruction
+ state_nxt_wrap = S_FETCH;
+ end
+ end
+ endcase
+ state_nxt = &bit_ctr ? state_nxt_wrap : state;
+ bit_ctr_nxt = &bit_ctr ? bit_ctr_nxt_wrap : bit_ctr + 4'h1;
+end
+
+// Start of day:
+//
+// - The only resettable flops are state, bit_ctr, and instr_cond_true.
+//
+// - We reset state/bit_ctr to a nonsequential fetch, and reset
+// instr_cond_true=0 (usually unreachable)
+//
+// - instr_cond_true=0 masks the fetch address to 0, regardless of PC
+//
+// - The first instruction must be `add pc, zero, #4` to initialise PC
+//
+// - You may then want to clear all the GPRs, though it's not necessary as
+// they will always be written before first read.
+
+always @ (posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ state <= S_PC_NONSEQ0;
+ bit_ctr <= 4'h6;
+ end else begin
+ state <= state_nxt;
+ bit_ctr <= bit_ctr_nxt;
+ end
+end
+
+// ----------------------------------------------------------------------------
+// Instruction shifter and early decode
+
+// Manually instantiate DFFEs, as otherwise we get mux + DFF which is larger
+
+wire shift_instr_reg = state == S_FETCH;
+
+whisk_flop_en instr_flop_u[15:0] (
+ .clk (clk),
+ .d ({mem_sdi_prev, instr[15:1]}),
+ .e (shift_instr_reg),
+ .q (instr)
+);
+
+// Decode condition and imm operand flags as the instruction comes in, so we
+// can use them to steer the state machine at the end of S_FETCH.
+
+reg instr_has_imm_operand_nxt;
+reg instr_cond_true_nxt;
+
+// From ALU:
+wire [7:0] condition_vec8;
+
+always @ (*) begin
+ instr_has_imm_operand_nxt = instr_has_imm_operand;
+ instr_cond_true_nxt = instr_cond_true;
+
+ if (instr_has_imm_operand && !instr_cond_true) begin
+ // In this case we must be in S_FETCH. Hold instr_cond_true for an
+ // additional fetch cycle so that the immediate operand is also
+ // dumped, but clear the operand flag so we don't loop forever.
+ if (&bit_ctr) begin
+ instr_has_imm_operand_nxt = 1'b0;
+ end
+ end else if (state == S_FETCH) begin
+ if (bit_ctr == (INSTR_RT_MSB + 1)) begin
+ // Grab rt as it goes past (this is why rt is not the MSBs!)
+ instr_has_imm_operand_nxt = instr[W_INSTR-1 -: 3] == 3'd6;
+ end
+ if (bit_ctr == (INSTR_COND_MSB + 1)) begin
+ // Decode condition as it goes past
+ instr_cond_true_nxt = condition_vec8[instr[W_INSTR-1 -: 3]];
+ end
+ end
+end
+
+// instr_cond_true must reset to 0, because we use it to recognise the first
+// fetch after reset. We don't care about instr_has_imm_operand, because it
+// is initialised during S_FETCH before first use.
+
+always @ (posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ instr_cond_true <= 1'b0;
+ end else begin
+ instr_cond_true <= instr_cond_true_nxt;
+ end
+end
+
+always @ (posedge clk) begin
+ instr_has_imm_operand <= instr_has_imm_operand_nxt;
+end
+
+// ----------------------------------------------------------------------------
+// Register file
+
+wire regfile_shift_l_nr;
+
+wire reg_rd_ql, reg_rd_qr;
+wire reg_rs_ql, reg_rs_qr;
+wire reg_rt_ql, reg_rt_qr;
+
+wire alu_result;
+
+wire ls_early_postdec = state == S_PC_NONSEQ1 && instr_op_ls &&
+ instr_op_ls_da && !instr_has_imm_operand;
+
+wire writeback_wen =
+ state == S_EXEC ||
+ state == S_LS_DATA && !instr_op_st_nld ||
+ state == S_PC_NONSEQ1 && ls_early_postdec ||
+ state == S_LS_IMMPD && instr_cond_true;
+
+wire writeback_data = state == S_LS_DATA ? mem_sdi_prev : alu_result;
+
+wire [INSTR_RD_MSB-INSTR_RD_LSB:0] writeback_reg =
+ instr_op_ls && state != S_LS_DATA ? instr_rs : instr_rd;
+
+whisk_regfile #(
+ .W (W_DATA),
+ .N (N_REGS)
+) regfile_u (
+ .clk (clk),
+ .l_nr (regfile_shift_l_nr),
+
+ .rd (writeback_reg),
+ .rd_ql (reg_rd_ql),
+ .rd_qr (reg_rd_qr),
+ .rd_wen (writeback_wen),
+ .rd_d (writeback_data),
+
+ .rs (instr_rs),
+ .rs_ql (reg_rs_ql),
+ .rs_qr (reg_rs_qr),
+
+ .rt (instr_rt),
+ .rt_ql (reg_rt_ql),
+ .rt_qr (reg_rt_qr)
+);
+
+// On every cycle, the GPRs are shifted or rotated either to the left or the
+// right. There is no shift enable, because enables cost money.
+//
+// - Normally we shift to right, and qr (rightmost flop in each register
+// chain) is the output. This lets us propagate carries serially.
+// Exceptions are: EXEC (instr: SRL/SRA only), LS_ADDR0 and LS_ADDR1.
+//
+// - For EXEC of SRL/SRA we reverse the GPR rotation to get the opposite shift
+// direction from a SLL. (See signal: alu_shift)
+//
+// - Total shift amount through LS_ADDR0/LS_ADDR1 must be a multiple of 16, to
+// avoid permanently rotating a register!
+//
+// - Total shift amount at cycle n, mod 2, is always n mod 2. (The total shift
+// amount always increments or decrements.) Get around this by using qr/ql
+// outputs of regfile.
+//
+// - Loads: Read address MSB-first (shift to left). MSB must be available on
+// final cycle of LS_ADDR0. LSB must be available on penultimate cycle of
+// LS_ADDR1, so that load data is available first cycle of LS_DATA. Shift
+// to left for last 2 cycles of ADDR0 and first 14 cycles of ADDR1, output
+// is qr. Jiggle back and forth for remaining cycles to keep 2-cycle shift
+// sum at 0.
+//
+// - Stores: Read address MSB-first (shift to left). LSB of address must be
+// available on final cycle of LS_ADDR1, store data follows immmediately in
+// LS_DATA. Rotate left for entirety of LS_ADDR1, output is ql.
+//
+// - Need to jiggle the register file during PC_NSEQ0 as this is not 16 cycles
+// long and we don't want to permanently rotate the register file
+
+wire instr_is_right_shift = instr_op == OP_SHIFT && !instr_rt[2];
+
+assign regfile_shift_l_nr =
+ state == S_PC_NONSEQ0 ? bit_ctr[0] :
+ state == S_EXEC && instr_is_right_shift ? 1'b1 :
+ state == S_LS_ADDR0 && !instr_op_st_nld ? (&bit_ctr[3:1] ? 1'b1 : bit_ctr[0]) :
+ state == S_LS_ADDR1 && !instr_op_st_nld ? (&bit_ctr[3:1] ? bit_ctr[0] : 1'b1) :
+ state == S_LS_ADDR1 && instr_op_st_nld ? 1'b1 : 1'b0;
+
+// ----------------------------------------------------------------------------
+// Program counter
+
+wire pc_l_nr;
+wire pc_dl;
+wire pc_qr;
+wire pc_dr;
+wire pc_ql;
+
+whisk_shiftreg_leftright #(
+ .W (16)
+) pc_u (
+ .clk (clk),
+ .l_nr (pc_l_nr),
+ .dl (pc_dl),
+ .dr (pc_dr),
+ .ql (pc_ql),
+ .qr (pc_qr)
+);
+
+// We increment PC at the following times, noting that at the beginning of
+// S_FETCH we do not know whether the instruction has an immediate, or
+// whether its condition is true:
+//
+// - S_FETCH: +2 (Note: if there is an immediate, and cond is false, we go
+// through S_LS_IMMPD to dump the immediate, so +4 total).
+//
+// - S_EXEC: +2 if there is an immediate, UNLESS instruction is a load/store
+// with post-decrement.
+//
+// - S_LS_IMMPD: +2 (only reachable for load/store with immediate
+// post-decrement, or for dumping second half of disabled instruction).
+// Note: these instructions need special handling because they fetch the
+// immediate twice, so PC needs to point to the immediate after S_EXEC.
+
+wire pc_increment =
+ state == S_FETCH ||
+ state == S_EXEC && instr_has_imm_operand && !(instr_op_ls && instr_op_ls_da) ||
+ state == S_LS_IMMPD;
+
+reg pc_ci;
+wire pc_co, pc_sum;
+
+assign {pc_co, pc_sum} = pc_qr + (~|bit_ctr[3:1] ? bit_ctr[0] && pc_increment : pc_ci);
+
+always @ (posedge clk) begin
+ pc_ci <= pc_co;
+end
+
+// Similar shift rules to register file shift rules for loads. LSB of addr is
+// available on q_r on the penultimate cycle of PC_NONSEQ1. Also jiggle the
+// PC during LS_ADDR0, as this state is not 16 cycles long, and we don't want
+// to permanently rotate the PC.
+
+wire pc_l_nr =
+ state == S_PC_NONSEQ0 ? (&bit_ctr[3:1] ? 1'b1 : bit_ctr[0]) :
+ state == S_PC_NONSEQ1 ? (&bit_ctr[3:1] ? bit_ctr[0] : 1'b1) :
+ state == S_LS_ADDR0 ? bit_ctr[0] : 1'b0;
+
+assign pc_dr = pc_ql;
+
+assign pc_dl =
+ state == S_FETCH ? pc_sum :
+ state == S_EXEC && instr_rd != 3'd7 ? pc_sum :
+ state == S_EXEC && instr_rd == 3'd7 ? alu_result :
+ state == S_LS_DATA && instr_rd == 3'd7 && !instr_op_st_nld ? mem_sdi_prev :
+ state == S_LS_IMMPD ? pc_sum : pc_qr;
+
+// ----------------------------------------------------------------------------
+// ALU
+
+wire alu_op_s =
+ instr_rs == 3'd7 ? pc_qr : reg_rs_qr;
+
+wire alu_op_t =
+ instr_rt == 3'd7 ? pc_qr :
+ instr_rt == 3'd6 ? mem_sdi_prev : reg_rt_qr;
+
+reg alu_ci;
+wire [1:0] alu_add = alu_op_s + alu_op_t + (~|bit_ctr ? 1'b0 : alu_ci);
+wire [1:0] alu_sub = alu_op_s + !alu_op_t + (~|bit_ctr ? 1'b1 : alu_ci);
+
+// Shift uses the ALU carry flop as a 1-cycle delay. SRL/SRA rotate the
+// regfile to the left, SLL rotates the regfile to the right, and the delay
+// produces a shift opposite to the regfile's rotation.
+
+wire [1:0] alu_shift = {
+ instr_is_right_shift ? reg_rs_ql : reg_rs_qr,
+ |bit_ctr ? alu_ci : reg_rs_qr && instr_rt[0]
+};
+
+wire alu_co;
+assign {alu_co, alu_result} =
+ state == S_LS_IMMPD ? alu_sub :
+ ls_early_postdec ? alu_sub :
+ // state == S_EXEC:
+ instr_op_ls && instr_op_ls_ib ? alu_add :
+ instr_op == OP_ADD ? alu_add :
+ instr_op == OP_SUB ? alu_sub :
+ instr_op == OP_AND ? alu_op_s && alu_op_t :
+ instr_op == OP_ANDN ? alu_op_s && !alu_op_t :
+ instr_op == OP_OR ? alu_op_s || alu_op_t :
+ instr_op == OP_SHIFT ? alu_shift :
+ instr_op == OP_INOUT ? ioport_sdi_prev : reg_rd_qr;
+
+always @ (posedge clk) begin
+ alu_ci <= alu_co;
+end
+
+// ----------------------------------------------------------------------------
+// Flags
+
+reg flag_z;
+reg flag_c;
+reg flag_n;
+
+wire update_flags = (state == S_EXEC || state == S_LS_DATA) && ~|instr_cond;
+
+// TODO sensible flags for load/store
+always @ (posedge clk) begin
+ if (update_flags) begin
+ flag_z <= (flag_z || ~|bit_ctr) && !alu_result;
+ flag_n <= alu_result;
+ flag_c <= alu_co;
+ end
+end
+
+assign condition_vec8 = {
+ !flag_z, flag_z,
+ !flag_c, flag_c,
+ !flag_n, flag_n,
+ 1'b1, 1'b1
+};
+
+// ----------------------------------------------------------------------------
+// Memory SPI controls
+
+// Deassert CSn before issuing a nonsequential address, only.
+assign mem_csn_next = bit_ctr == 4'h6 && (
+ state == S_PC_NONSEQ0 ||
+ state == S_LS_ADDR0
+);
+
+// Pedal to the metal on SCK except when pulling CSn for a nonsequential
+// access, or when executing an instruction with no immediate.
+assign mem_sck_en_next = !(
+ mem_csn_next ||
+ state == (&bit_ctr[3:1] ? S_FETCH : S_EXEC) && !instr_has_imm_operand && instr_cond_true
+);
+
+// ldr issues addresses one cycle earlier than str, due to in->out delay.
+// Note: SPI commands are MSB-first (the commands here are 03h and 02h).
+localparam [15:0] SPI_INSTR_READ = 16'hc000 >> 1;
+localparam [15:0] SPI_INSTR_WRITE = 16'h8000;
+
+// See notes on shift direction in register file section. We are shifting to
+// left to get MSB-first addr, but since load addresses are a cycle early,
+// they end up using the qr output to get even register lag on an odd cycle.
+wire ls_addr = instr_op_st_nld ? reg_rs_ql : reg_rs_qr;
+
+wire mem_sdo_ls_addr0 =
+ instr_op_st_nld ? SPI_INSTR_WRITE[bit_ctr] :
+ &bit_ctr ? ls_addr : SPI_INSTR_READ[bit_ctr];
+
+assign mem_sdo_next =
+ state == S_PC_NONSEQ0 ? (&bit_ctr ? pc_qr : SPI_INSTR_READ[bit_ctr]) :
+ state == S_PC_NONSEQ1 ? pc_qr && instr_cond_true :
+ state == S_LS_ADDR0 ? mem_sdo_ls_addr0 :
+ state == S_LS_ADDR1 ? ls_addr :
+ state == S_LS_DATA ? reg_rd_qr : 1'b0;
+
+// ----------------------------------------------------------------------------
+// IO port
+
+// Expected hardware is a 1x 8-bit PISO, and 2x 8-bit SIPO shift registers:
+//
+// - OUT: Clock out 16 bits from rt[15:0]/imm[15:0], then pulse latch_o high.
+//
+// - IN: Clock 8 bits into rd[15:8], with latch_i high for the first clock.
+//
+// The IN interface is still driven when executing an OUT, with more clocks.
+// Abusable for 6 extra inputs if a second PISO register is chained.
+//
+// rt[13:6] is actually clocked out on an IN, there's just no latch_o pulse.
+// Abusable to drive longer SIPO chains using multiple INs and a final OUT.
+
+wire exec_io_instr = state == S_EXEC && instr_op == OP_INOUT;
+wire io_instr_out = (instr_rs & (OP2_OUT | OP2_IN)) == OP2_OUT;
+
+// The instruction is still valid on the first cycle of FETCH. This lets us
+// latch outputs *after* the last clock pulse, without spending a flop.
+assign ioport_latch_o_next = state == S_FETCH && ~|bit_ctr &&
+ instr_op == OP_INOUT && io_instr_out && instr_cond_true;
+
+assign ioport_latch_i_next = exec_io_instr && bit_ctr == 4'h6;
+
+assign ioport_sdo_next = exec_io_instr && alu_op_t;
+
+assign ioport_sck_en_next = exec_io_instr && (
+ (bit_ctr >= 4'h6 && bit_ctr < 4'he) ||
+ io_instr_out
+);
+
+endmodule
+
+// ============================================================================
+// Module whisk_regfile: a register file of multiple shift registers, with 3
+// read ports (rd/rs/rt) and one write port (rd).
+// ============================================================================
+
+// No enable, so try to do things in multiples of 16 cycles. Registers not
+// being written to are recirculated.
+//
+// qr is the value of the rightmost flop in a shift register (usually what you
+// want when shifting out to right) and ql is the value of the leftmost flop
+// in a shift register (usually what you want when shifting out to left).
+//
+// Out-of-range indices read as 0, and ignore writes.
+
+module whisk_regfile #(
+ parameter W = 16,
+ parameter N = 6
+) (
+ input wire clk,
+ input wire l_nr,
+
+ input wire [$clog2(N)-1:0] rd,
+ output wire rd_ql,
+ output wire rd_qr,
+ input wire rd_wen,
+ input wire rd_d,
+
+ input wire [$clog2(N)-1:0] rs,
+ output wire rs_ql,
+ output wire rs_qr,
+
+ input wire [$clog2(N)-1:0] rt,
+ output wire rt_ql,
+ output wire rt_qr
+);
+
+localparam N_PADDED = 1 << $clog2(N);
+
+wire [N-1:0] dl;
+wire [N-1:0] dr;
+wire [N_PADDED-1:0] ql;
+wire [N_PADDED-1:0] qr;
+
+assign rd_ql = ql[rd];
+assign rs_ql = ql[rs];
+assign rt_ql = ql[rt];
+
+assign rd_qr = qr[rd];
+assign rs_qr = qr[rs];
+assign rt_qr = qr[rt];
+
+genvar g;
+generate
+for (g = 0; g < N_PADDED; g = g + 1) begin: loop_gprs
+ if (g >= N) begin: gpr_tieoff
+
+ assign ql[g] = 1'b0;
+ assign qr[g] = 1'b0;
+
+ end else begin: gpr_shifter
+
+ // Recirculate unless this register is addressed as rd.
+ assign dl[g] = rd_wen && rd == g ? rd_d : qr[g];
+ assign dr[g] = rd_wen && rd == g ? rd_d : ql[g];
+
+ whisk_shiftreg_leftright #(
+ .W (W)
+ ) reg_u (
+ .clk (clk),
+ .l_nr (l_nr),
+ .dl (dl[g]),
+ .ql (ql[g]),
+ .dr (dr[g]),
+ .qr (qr[g])
+ );
+
+ end
+end
+endgenerate
+
+endmodule
+
+// ============================================================================
+// Module whisk_shiftreg_leftright: a shift register that always shifts left
+// or right each cycle.
+// ============================================================================
+
+// Note there is no enable because the underlying scan flops do not have an
+// enable (there is an enable version, but it's larger, and more routing
+// required!). If you don't want to shift, just shift back and forth for an
+// even number of cycles, or do a full loop :) Shifting by an odd number of
+// bits in an even number of cycles requires a delay flop to be patched in.
+//
+// dl and ql are the leftmost inputs and outputs. If l_nr is low (right), ql
+// becomes dl on every posedge of clk. (Yes, it's confusing!)
+//
+// dr and qr are the rightmost inputs and outputs. If l_nr is high (left), qr
+// becomes dr on every posedge of clk.
+
+module whisk_shiftreg_leftright #(
+ parameter W = 16
+) (
+ input wire clk,
+ input wire l_nr,
+ input wire dl,
+ input wire dr,
+ output wire ql,
+ output wire qr
+);
+
+wire [W+1:0] chain_q;
+
+assign chain_q[0 ] = dr;
+assign chain_q[W + 1] = dl;
+
+assign qr = chain_q[1];
+assign ql = chain_q[W];
+
+genvar g;
+generate
+for (g = 1; g < W + 1; g = g + 1) begin: shift_stage
+ // Shift-to-left means select the input to your right, and vice versa.
+ whisk_flop_scanmux flop_u (
+ .clk (clk),
+ .sel (l_nr),
+ .d ({chain_q[g - 1], chain_q[g + 1]}),
+ .q (chain_q[g])
+ );
+end
+endgenerate
+
+endmodule
+
+// ============================================================================
+// Module whisk_flop_scanmux: a flop with a mux on its input. Usually reserved
+// for DFT scan insertion, but we don't need that where we're going >:)
+// ============================================================================
+
+module whisk_flop_scanmux (
+ input wire clk,
+ input wire sel,
+ input wire [1:0] d,
+ output wire q
+);
+
+`ifdef WHISK_CELLS_SKY130
+
+// (scanchain in TT2 uses sky130_fd_sc_hd__sdfxtp, a simple flop with scan
+// mux. An enable version, sky130_fd_sc_hd__sedfxtp, is also available, but
+// this is significantly larger. Instantiate the unit-drive version because
+// we have a ridiculously long clock period; not sure whether the backend is
+// allowed to change the drive.)
+
+sky130_fd_sc_hd__sdfxtp_1 sdff_u (
+ .CLK (clk),
+ .D (d[0]),
+ .SCD (d[1]),
+ .SCE (sel),
+ .Q (q),
+ .VPWR (1'b1),
+ .VGND (1'b0)
+);
+
+`else
+
+// Synthesisable model
+
+reg q_r;
+always @ (posedge clk) begin
+ q_r <= d[sel];
+end
+
+assign q = q_r;
+
+`endif
+
+endmodule
+
+// ============================================================================
+// Module whisk_flop_en: a flop with an input enable (DFFE). For some reason
+// these are not mapped automatically, so we get a DFF, a mux and two buffers
+// ============================================================================
+
+module whisk_flop_en (
+ input wire clk,
+ input wire d,
+ input wire e,
+ output wire q
+);
+
+`ifdef WHISK_CELLS_SKY130
+
+sky130_fd_sc_hd__edfxtp_1 dffe_u (
+ .CLK (clk),
+ .D (d),
+ .DE (e),
+ .Q (q),
+ .VPWR (1'b1),
+ .VGND (1'b0)
+);
+
+`else
+
+// Synthesisable model
+
+reg q_r;
+always @ (posedge clk) begin
+ if (e) begin
+ q_r <= d;
+ end
+end
+
+assign q = q_r;
+
+`endif
+
+endmodule
+// ============================================================================
+// Module whisk_spi_serdes: handle the timing of the SPI interface, and
+// provide a slightly abstracted interface to the whisk core, with all
+// signals on posedge of clk.
+// ============================================================================
+
+module whisk_spi_serdes(
+ input wire clk,
+ input wire rst_n,
+
+ // Core
+ input wire sdo,
+ input wire sck_en,
+ input wire csn,
+ output wire sdi,
+
+ // IOs
+ output wire padout_sck,
+ output wire padout_csn,
+ output wire padout_sdo,
+ input wire padin_sdi
+);
+
+// ----------------------------------------------------------------------------
+// Output paths
+
+reg sdo_r;
+reg sck_en_r;
+reg csn_r;
+
+always @ (posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ sdo_r <= 1'b0;
+ csn_r <= 1'b1;
+ sck_en_r <= 1'b0;
+ end else begin
+ sdo_r <= sdo;
+ csn_r <= csn;
+ sck_en_r <= sck_en;
+ end
+end
+
+assign padout_sdo = sdo_r;
+assign padout_csn = csn_r;
+
+// Through-path for clock input to SCK output. TODO clock gating cell
+// required? This is sampled by the scan flops at the tile output.
+assign padout_sck = sck_en_r && !clk;
+
+// ----------------------------------------------------------------------------
+// Input paths
+
+`ifdef WHISK_CELLS_SKY130
+
+// ASIC version
+
+// TODO find a suitable delay buffer cell for hold buffering, and decide how to
+// dimension it against i[7:0] skew
+
+// TODO find a suitable latch cell (possibly sky130_fd_sc_hd__dlxtp)
+
+wire padin_sdi_delay = padin_sdi;
+
+reg sdi_latch;
+
+always @ (*) begin
+ if (clk) begin
+ sdi_latch <= padin_sdi_delay;
+ end
+end
+
+assign sdi = sdi_latch;
+
+`else
+
+// Dodgy sim-only version
+
+reg padin_sdi_reg;
+always @ (negedge clk) begin
+ padin_sdi_reg <= padin_sdi;
+end
+
+// FIXME there is something I don't understand here with the CXXRTL delta cycles
+// assign sdi = padin_sdi_reg;
+assign sdi = padin_sdi;
+
+`endif
+
+endmodule
+
+// ============================================================================
+// Module whisk_ioport_serdes: similar to whisk_spi_serdes, but for the
+// shift-register-based IO port.
+// ============================================================================
+
+module whisk_ioport_serdes(
+ input wire clk,
+ input wire rst_n,
+
+ // Core
+ input wire sdo,
+ input wire sck_en,
+ input wire latch_i,
+ input wire latch_o,
+ output wire sdi,
+
+ // IOs
+ output wire padout_sdo,
+ output wire padout_sck,
+ output wire padout_latch_i,
+ output wire padout_latch_o,
+ input wire padin_sdi
+);
+
+// ----------------------------------------------------------------------------
+// Output paths
+
+reg sdo_r;
+reg sck_en_r;
+reg latch_i_r;
+reg latch_o_r;
+
+always @ (posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ sdo_r <= 1'b0;
+ sck_en_r <= 1'b0;
+ latch_i_r <= 1'b0;
+ latch_o_r <= 1'b0;
+ end else begin
+ sdo_r <= sdo;
+ sck_en_r <= sck_en;
+ latch_i_r <= latch_i;
+ latch_o_r <= latch_o;
+ end
+end
+
+assign padout_sdo = sdo_r;
+assign padout_latch_i = latch_i_r;
+assign padout_latch_o = latch_o_r;
+
+// TODO clock gating cell?
+assign padout_sck = sck_en_r && !clk;
+
+// ----------------------------------------------------------------------------
+// Input paths
+
+// FIXME this is actually different from SPI, right? Probably transitions on
+// posedge? Need to find some actual datasheets for candidate shift
+// registers.
+
+`ifdef WHISK_CELLS_SKY130
+
+// ASIC version
+
+// TODO find a suitable delay buffer cell for hold buffering, and decide how to
+// dimension it against i[7:0] skew
+
+// TODO find a suitable latch cell (possibly sky130_fd_sc_hd__dlxtp)
+
+wire padin_sdi_delay = padin_sdi;
+
+reg sdi_latch;
+
+always @ (*) begin
+ if (clk) begin
+ sdi_latch <= padin_sdi_delay;
+ end
+end
+
+assign sdi = sdi_latch;
+
+`else
+
+// Dodgy sim-only version
+
+reg padin_sdi_reg;
+always @ (negedge clk) begin
+ padin_sdi_reg <= padin_sdi;
+end
+
+assign sdi = padin_sdi_reg;
+
+`endif
+
+endmodule
+
+// ============================================================================
+//
+// _ _ _
+// | | (_) | |
+// __ _| |__ _ ___| | __
+// \ \ /\ / / '_ \| / __| |/ /
+// \ V V /| | | | \__ \ <
+// \_/\_/ |_| |_|_|___/_|\_\
+//
+//
+// When I was 16 I designed a 7400-series breadboard processor called Fork,
+// with a language called Spoon. Now I'm 26 and I'm designing a processor
+// called Whisk. I wonder what I'll do when I grow up.
+//
+// Many mistakes were made in this ISA. What did you think? My aim with this
+// version of Whisk is to run enough software to discover exactly why my
+// instruction set is bad. Hopefully Tiny Tapeout 3 will bring faster IOs,
+// with 2D muxing instead of a scan chain, and then I can try getting some
+// serious software running on Whisk v2, at a few MHz instead of 12 kHz.
diff --git a/verilog/rtl/user_module_341178154799333971.v b/verilog/rtl/user_module_341178154799333971.v
new file mode 100644
index 0000000..1f52ace
--- /dev/null
+++ b/verilog/rtl/user_module_341178154799333971.v
@@ -0,0 +1,274 @@
+/* Automatically generated from https://wokwi.com/projects/341178154799333971 */
+
+`default_nettype none
+
+module user_module_341178154799333971(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[0];
+ wire net2 = io_in[1];
+ wire net3 = io_in[2];
+ wire net4;
+ wire net5;
+ wire net6;
+ wire net7;
+ wire net8;
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12 = 1'b0;
+ wire net13 = 1'b1;
+ wire net14 = 1'b1;
+ wire net15;
+ wire net16;
+ wire net17;
+ wire net18;
+ wire net19;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
+ wire net49;
+ wire net50;
+ wire net51;
+ wire net52;
+ wire net53;
+ wire net54;
+ wire net55;
+ wire net56;
+ wire net57;
+ wire net58;
+
+ assign io_out[0] = net4;
+ assign io_out[1] = net5;
+ assign io_out[2] = net6;
+ assign io_out[3] = net7;
+ assign io_out[4] = net8;
+ assign io_out[5] = net9;
+ assign io_out[6] = net10;
+ assign io_out[7] = net11;
+
+ xor_cell gate3 (
+ .a (net15),
+ .b (net6),
+ .out (net16)
+ );
+ mux_cell mux1 (
+ .a (net17),
+ .b (net2),
+ .sel (net3),
+ .out (net18)
+ );
+ dff_cell flipflop2 (
+ .d (net18),
+ .clk (net1),
+ .q (net19),
+ .notq (net20)
+ );
+ dff_cell flipflop3 (
+ .d (net19),
+ .clk (net1),
+ .q (net21),
+ .notq (net22)
+ );
+ dff_cell flipflop4 (
+ .d (net21),
+ .clk (net1),
+ .q (net23),
+ .notq (net24)
+ );
+ dff_cell flipflop5 (
+ .d (net23),
+ .clk (net1),
+ .q (net25),
+ .notq (net26)
+ );
+ dff_cell flipflop6 (
+ .d (net27),
+ .clk (net1),
+ .q (net28),
+ .notq (net29)
+ );
+ dff_cell flipflop7 (
+ .d (net25),
+ .clk (net1),
+ .q (net27),
+ .notq (net30)
+ );
+ dff_cell flipflop8 (
+ .d (net28),
+ .clk (net1),
+ .q (net31),
+ .notq (net32)
+ );
+ dff_cell flipflop9 (
+ .d (net31),
+ .clk (net1),
+ .q (net33),
+ .notq (net34)
+ );
+ dff_cell flipflop10 (
+ .d (net33),
+ .clk (net1),
+ .q (net4),
+ .notq (net35)
+ );
+ dff_cell flipflop11 (
+ .d (net4),
+ .clk (net1),
+ .q (net5),
+ .notq (net36)
+ );
+ dff_cell flipflop12 (
+ .d (net5),
+ .clk (net1),
+ .q (net6),
+ .notq (net37)
+ );
+ dff_cell flipflop13 (
+ .d (net6),
+ .clk (net1),
+ .q (net7),
+ .notq (net38)
+ );
+ dff_cell flipflop14 (
+ .d (net7),
+ .clk (net1),
+ .q (net8),
+ .notq (net39)
+ );
+ dff_cell flipflop15 (
+ .d (net8),
+ .clk (net1),
+ .q (net9),
+ .notq (net40)
+ );
+ dff_cell flipflop16 (
+ .d (net9),
+ .clk (net1),
+ .q (net10),
+ .notq (net41)
+ );
+ xor_cell gate7 (
+ .a (net42),
+ .b (net8),
+ .out (net15)
+ );
+ xor_cell gate8 (
+ .a (net11),
+ .b (net9),
+ .out (net42)
+ );
+ dff_cell flipflop1 (
+ .d (net10),
+ .clk (net1),
+ .q (net11),
+ .notq (net43)
+ );
+ or_cell gate1 (
+ .a (net44),
+ .b (net16),
+ .out (net17)
+ );
+ and_cell gate2 (
+ .a (net45),
+ .b (net46),
+ .out (net47)
+ );
+ and_cell gate4 (
+ .a (net22),
+ .b (net20),
+ .out (net46)
+ );
+ and_cell gate5 (
+ .a (net26),
+ .b (net24),
+ .out (net45)
+ );
+ and_cell gate6 (
+ .a (net29),
+ .b (net30),
+ .out (net48)
+ );
+ and_cell gate9 (
+ .a (net34),
+ .b (net32),
+ .out (net49)
+ );
+ and_cell gate10 (
+ .a (net36),
+ .b (net35),
+ .out (net50)
+ );
+ and_cell gate11 (
+ .a (net38),
+ .b (net37),
+ .out (net51)
+ );
+ and_cell gate12 (
+ .a (net40),
+ .b (net39),
+ .out (net52)
+ );
+ and_cell gate13 (
+ .a (net43),
+ .b (net41),
+ .out (net53)
+ );
+ and_cell gate14 (
+ .a (net49),
+ .b (net48),
+ .out (net54)
+ );
+ and_cell gate15 (
+ .a (net51),
+ .b (net50),
+ .out (net55)
+ );
+ and_cell gate16 (
+ .a (net53),
+ .b (net52),
+ .out (net56)
+ );
+ and_cell gate17 (
+ .a (net54),
+ .b (net47),
+ .out (net57)
+ );
+ and_cell gate19 (
+ .a (net56),
+ .b (net55),
+ .out (net58)
+ );
+ and_cell gate20 (
+ .a (net58),
+ .b (net57),
+ .out (net44)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_341277789473735250.v b/verilog/rtl/user_module_341277789473735250.v
new file mode 100644
index 0000000..be7cc3f
--- /dev/null
+++ b/verilog/rtl/user_module_341277789473735250.v
@@ -0,0 +1,763 @@
+/* Automatically generated from https://wokwi.com/projects/341277789473735250 */
+
+`default_nettype none
+
+module user_module_341277789473735250(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[0];
+ wire net2 = io_in[1];
+ wire net3 = io_in[2];
+ wire net4 = io_in[3];
+ wire net5 = io_in[4];
+ wire net6 = io_in[5];
+ wire net7 = io_in[6];
+ wire net8 = io_in[7];
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15;
+ wire net16;
+ wire net17 = 1'b0;
+ wire net18 = 1'b1;
+ wire net19;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
+ wire net49;
+ wire net50;
+ wire net51;
+ wire net52;
+ wire net53;
+ wire net54;
+ wire net55;
+ wire net56;
+ wire net57;
+ wire net58;
+ wire net59;
+ wire net60;
+ wire net61;
+ wire net62;
+ wire net63;
+ wire net64;
+ wire net65;
+ wire net66;
+ wire net67;
+ wire net68;
+ wire net69;
+ wire net70;
+ wire net71;
+ wire net72;
+ wire net73;
+ wire net74;
+ wire net75;
+ wire net76;
+ wire net77;
+ wire net78;
+ wire net79;
+ wire net80;
+ wire net81;
+ wire net82;
+ wire net83;
+ wire net84;
+ wire net85;
+ wire net86;
+ wire net87;
+ wire net88;
+ wire net89;
+ wire net90;
+ wire net91;
+ wire net92;
+ wire net93;
+ wire net94;
+ wire net95;
+ wire net96;
+ wire net97;
+ wire net98;
+ wire net99;
+ wire net100;
+ wire net101;
+ wire net102;
+ wire net103;
+ wire net104;
+ wire net105;
+ wire net106;
+ wire net107;
+ wire net108;
+ wire net109;
+ wire net110;
+ wire net111;
+ wire net112;
+ wire net113;
+ wire net114;
+ wire net115;
+ wire net116;
+ wire net117;
+ wire net118;
+ wire net119;
+ wire net120;
+ wire net121;
+ wire net122;
+ wire net123;
+ wire net124;
+ wire net125;
+ wire net126;
+ wire net127;
+ wire net128;
+ wire net129;
+ wire net130;
+ wire net131;
+ wire net132;
+ wire net133;
+ wire net134;
+ wire net135;
+
+ assign io_out[0] = net9;
+ assign io_out[1] = net10;
+ assign io_out[2] = net11;
+ assign io_out[3] = net12;
+ assign io_out[4] = net13;
+ assign io_out[5] = net14;
+ assign io_out[6] = net15;
+ assign io_out[7] = net16;
+
+ or_cell gate7 (
+ .a (net19),
+ .b (net20),
+ .out (net15)
+ );
+ or_cell gate9 (
+ .a (net21),
+ .b (net22),
+ .out (net14)
+ );
+ or_cell gate10 (
+ .a (net23),
+ .b (net24),
+ .out (net13)
+ );
+ or_cell gate11 (
+ .a (net25),
+ .b (net26),
+ .out (net11)
+ );
+ or_cell gate12 (
+ .a (net27),
+ .b (net28),
+ .out (net12)
+ );
+ or_cell gate13 (
+ .a (net29),
+ .b (net30),
+ .out (net10)
+ );
+ or_cell gate14 (
+ .a (net31),
+ .b (net32),
+ .out (net9)
+ );
+ or_cell gate17 (
+ .a (net22),
+ .b (net20),
+ .out (net28)
+ );
+ or_cell gate18 (
+ .a (net20),
+ .b (net22),
+ .out (net24)
+ );
+ or_cell gate19 (
+ .a (net20),
+ .b (net33),
+ .out (net30)
+ );
+ or_cell gate20 (
+ .a (net34),
+ .b (net22),
+ .out (net26)
+ );
+ or_cell gate21 (
+ .a (net20),
+ .b (net22),
+ .out (net32)
+ );
+ or_cell gate22 (
+ .a (net34),
+ .b (net22),
+ .out (net33)
+ );
+ or_cell gate8 (
+ .a (net35),
+ .b (net36),
+ .out (net27)
+ );
+ or_cell gate23 (
+ .a (net37),
+ .b (net38),
+ .out (net21)
+ );
+ or_cell gate24 (
+ .a (net37),
+ .b (net38),
+ .out (net23)
+ );
+ or_cell gate25 (
+ .a (net37),
+ .b (net38),
+ .out (net25)
+ );
+ or_cell gate26 (
+ .a (net39),
+ .b (net40),
+ .out (net19)
+ );
+ or_cell gate27 (
+ .a (net37),
+ .b (net38),
+ .out (net29)
+ );
+ or_cell gate28 (
+ .a (net41),
+ .b (net42),
+ .out (net31)
+ );
+ or_cell gate15 (
+ .a (net37),
+ .b (net43),
+ .out (net36)
+ );
+ or_cell gate16 (
+ .a (net43),
+ .b (net44),
+ .out (net39)
+ );
+ or_cell gate29 (
+ .a (net37),
+ .b (net38),
+ .out (net44)
+ );
+ or_cell gate30 (
+ .a (net37),
+ .b (net38),
+ .out (net41)
+ );
+ or_cell gate31 (
+ .a (net45),
+ .b (net46),
+ .out (net22)
+ );
+ or_cell gate32 (
+ .a (net47),
+ .b (net48),
+ .out (net34)
+ );
+ or_cell gate33 (
+ .a (net49),
+ .b (net50),
+ .out (net20)
+ );
+ or_cell gate34 (
+ .a (net51),
+ .b (net52),
+ .out (net40)
+ );
+ or_cell gate35 (
+ .a (net53),
+ .b (net54),
+ .out (net35)
+ );
+ or_cell gate39 (
+ .a (net55),
+ .b (net56),
+ .out (net42)
+ );
+ and_cell gate40 (
+ .a (net2),
+ .b (net57),
+ .out (net58)
+ );
+ and_cell gate41 (
+ .a (net2),
+ .b (net59),
+ .out (net60)
+ );
+ and_cell gate42 (
+ .a (net2),
+ .b (net61),
+ .out (net62)
+ );
+ and_cell gate43 (
+ .a (net2),
+ .b (net63),
+ .out (net64)
+ );
+ and_cell gate44 (
+ .a (net3),
+ .b (net4),
+ .out (net57)
+ );
+ and_cell gate45 (
+ .a (net65),
+ .b (net4),
+ .out (net59)
+ );
+ not_cell gate46 (
+ .in (net3),
+ .out (net65)
+ );
+ and_cell gate47 (
+ .a (net3),
+ .b (net66),
+ .out (net61)
+ );
+ not_cell gate48 (
+ .in (net4),
+ .out (net66)
+ );
+ xor_cell gate50 (
+ .a (net7),
+ .b (net8),
+ .out (net67)
+ );
+ and_cell gate51 (
+ .a (net7),
+ .b (net68),
+ .out (net69)
+ );
+ not_cell gate52 (
+ .in (net8),
+ .out (net68)
+ );
+ and_cell gate53 (
+ .a (net58),
+ .b (net70),
+ .out (net71)
+ );
+ and_cell gate54 (
+ .a (net58),
+ .b (net72),
+ .out (net73)
+ );
+ and_cell gate55 (
+ .a (net58),
+ .b (net74),
+ .out (net46)
+ );
+ and_cell gate56 (
+ .a (net58),
+ .b (net75),
+ .out (net48)
+ );
+ and_cell gate57 (
+ .a (net58),
+ .b (net76),
+ .out (net50)
+ );
+ or_cell gate58 (
+ .a (net77),
+ .b (net71),
+ .out (net54)
+ );
+ or_cell gate59 (
+ .a (net78),
+ .b (net73),
+ .out (net52)
+ );
+ and_cell gate61 (
+ .a (net79),
+ .b (net69),
+ .out (net70)
+ );
+ and_cell gate62 (
+ .a (net1),
+ .b (net67),
+ .out (net79)
+ );
+ and_cell gate63 (
+ .a (net80),
+ .b (net67),
+ .out (net81)
+ );
+ and_cell gate64 (
+ .a (net81),
+ .b (net69),
+ .out (net76)
+ );
+ and_cell gate65 (
+ .a (net80),
+ .b (net67),
+ .out (net82)
+ );
+ and_cell gate66 (
+ .a (net1),
+ .b (net67),
+ .out (net83)
+ );
+ or_cell gate67 (
+ .a (net83),
+ .b (net70),
+ .out (net72)
+ );
+ and_cell gate68 (
+ .a (net84),
+ .b (net85),
+ .out (net74)
+ );
+ not_cell gate69 (
+ .in (net69),
+ .out (net85)
+ );
+ and_cell gate70 (
+ .a (net80),
+ .b (net86),
+ .out (net84)
+ );
+ not_cell gate71 (
+ .in (net67),
+ .out (net86)
+ );
+ and_cell gate72 (
+ .a (net82),
+ .b (net87),
+ .out (net75)
+ );
+ not_cell gate73 (
+ .in (net69),
+ .out (net87)
+ );
+ xor_cell gate74 (
+ .a (net6),
+ .b (net8),
+ .out (net88)
+ );
+ xor_cell gate75 (
+ .a (net5),
+ .b (net7),
+ .out (net89)
+ );
+ not_cell gate76 (
+ .in (net89),
+ .out (net90)
+ );
+ not_cell gate77 (
+ .in (net88),
+ .out (net91)
+ );
+ and_cell gate78 (
+ .a (net90),
+ .b (net91),
+ .out (net92)
+ );
+ or_cell gate79 (
+ .a (net93),
+ .b (net94),
+ .out (net95)
+ );
+ and_cell gate80 (
+ .a (net96),
+ .b (net6),
+ .out (net93)
+ );
+ not_cell gate81 (
+ .in (net8),
+ .out (net97)
+ );
+ and_cell gate82 (
+ .a (net98),
+ .b (net5),
+ .out (net99)
+ );
+ not_cell gate83 (
+ .in (net7),
+ .out (net98)
+ );
+ or_cell gate84 (
+ .a (net100),
+ .b (net101),
+ .out (net102)
+ );
+ and_cell gate85 (
+ .a (net103),
+ .b (net104),
+ .out (net101)
+ );
+ not_cell gate86 (
+ .in (net6),
+ .out (net103)
+ );
+ and_cell gate87 (
+ .a (net7),
+ .b (net8),
+ .out (net104)
+ );
+ not_cell gate88 (
+ .in (net5),
+ .out (net105)
+ );
+ not_cell gate89 (
+ .in (net62),
+ .out (net106)
+ );
+ and_cell gate90 (
+ .a (net106),
+ .b (net8),
+ .out (net107)
+ );
+ and_cell gate91 (
+ .a (net62),
+ .b (net6),
+ .out (net108)
+ );
+ and_cell gate92 (
+ .a (net106),
+ .b (net7),
+ .out (net109)
+ );
+ and_cell gate93 (
+ .a (net62),
+ .b (net5),
+ .out (net110)
+ );
+ or_cell gate94 (
+ .a (net110),
+ .b (net109),
+ .out (net111)
+ );
+ or_cell gate95 (
+ .a (net108),
+ .b (net107),
+ .out (net112)
+ );
+ xor_cell gate96 (
+ .a (net111),
+ .b (net112),
+ .out (net113)
+ );
+ and_cell gate97 (
+ .a (net111),
+ .b (net112),
+ .out (net114)
+ );
+ and_cell gate99 (
+ .a (net115),
+ .b (net116),
+ .out (net77)
+ );
+ and_cell gate100 (
+ .a (net115),
+ .b (net117),
+ .out (net78)
+ );
+ and_cell gate101 (
+ .a (net115),
+ .b (net118),
+ .out (net56)
+ );
+ and_cell gate102 (
+ .a (net115),
+ .b (net119),
+ .out (net45)
+ );
+ and_cell gate103 (
+ .a (net115),
+ .b (net120),
+ .out (net47)
+ );
+ and_cell gate104 (
+ .a (net115),
+ .b (net121),
+ .out (net49)
+ );
+ and_cell gate105 (
+ .a (net1),
+ .b (net113),
+ .out (net117)
+ );
+ and_cell gate106 (
+ .a (net1),
+ .b (net122),
+ .out (net116)
+ );
+ and_cell gate107 (
+ .a (net80),
+ .b (net122),
+ .out (net119)
+ );
+ and_cell gate108 (
+ .a (net80),
+ .b (net113),
+ .out (net120)
+ );
+ and_cell gate109 (
+ .a (net80),
+ .b (net114),
+ .out (net121)
+ );
+ and_cell gate110 (
+ .a (net1),
+ .b (net114),
+ .out (net118)
+ );
+ or_cell gate111 (
+ .a (net62),
+ .b (net60),
+ .out (net115)
+ );
+ and_cell gate112 (
+ .a (net64),
+ .b (net123),
+ .out (net53)
+ );
+ and_cell gate113 (
+ .a (net64),
+ .b (net124),
+ .out (net51)
+ );
+ and_cell gate114 (
+ .a (net64),
+ .b (net125),
+ .out (net55)
+ );
+ and_cell gate115 (
+ .a (net64),
+ .b (net126),
+ .out (net37)
+ );
+ and_cell gate116 (
+ .a (net64),
+ .b (net127),
+ .out (net43)
+ );
+ and_cell gate117 (
+ .a (net64),
+ .b (net128),
+ .out (net38)
+ );
+ and_cell gate118 (
+ .a (net1),
+ .b (net95),
+ .out (net123)
+ );
+ and_cell gate119 (
+ .a (net1),
+ .b (net92),
+ .out (net124)
+ );
+ and_cell gate120 (
+ .a (net1),
+ .b (net102),
+ .out (net125)
+ );
+ and_cell gate121 (
+ .a (net80),
+ .b (net95),
+ .out (net126)
+ );
+ and_cell gate122 (
+ .a (net80),
+ .b (net92),
+ .out (net127)
+ );
+ and_cell gate123 (
+ .a (net80),
+ .b (net102),
+ .out (net128)
+ );
+ not_cell gate1 (
+ .in (net1),
+ .out (net80)
+ );
+ and_cell gate2 (
+ .a (net2),
+ .b (net1),
+ .out (net16)
+ );
+ or_cell gate3 (
+ .a (net3),
+ .b (net4),
+ .out (net129)
+ );
+ not_cell gate4 (
+ .in (net129),
+ .out (net63)
+ );
+ or_cell gate5 (
+ .a (net111),
+ .b (net112),
+ .out (net130)
+ );
+ not_cell gate6 (
+ .in (net130),
+ .out (net122)
+ );
+ and_cell gate36 (
+ .a (net97),
+ .b (net131),
+ .out (net132)
+ );
+ or_cell gate37 (
+ .a (net99),
+ .b (net132),
+ .out (net94)
+ );
+ and_cell gate38 (
+ .a (net5),
+ .b (net6),
+ .out (net131)
+ );
+ and_cell gate49 (
+ .a (net97),
+ .b (net98),
+ .out (net96)
+ );
+ or_cell gate60 (
+ .a (net133),
+ .b (net134),
+ .out (net100)
+ );
+ and_cell gate98 (
+ .a (net105),
+ .b (net135),
+ .out (net133)
+ );
+ and_cell gate124 (
+ .a (net105),
+ .b (net7),
+ .out (net134)
+ );
+ and_cell gate125 (
+ .a (net103),
+ .b (net8),
+ .out (net135)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_341423712597181012.v b/verilog/rtl/user_module_341423712597181012.v
new file mode 100644
index 0000000..fa5de54
--- /dev/null
+++ b/verilog/rtl/user_module_341423712597181012.v
@@ -0,0 +1,186 @@
+/* Automatically generated from https://wokwi.com/projects/341423712597181012 */
+
+`default_nettype none
+
+module user_module_341423712597181012(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[0];
+ wire net2 = io_in[1];
+ wire net3 = io_in[2];
+ wire net4 = io_in[3];
+ wire net5 = io_in[4];
+ wire net6 = io_in[5];
+ wire net7 = io_in[6];
+ wire net8 = io_in[7];
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13 = 1'b0;
+ wire net14 = 1'b1;
+ wire net15 = 1'b1;
+ wire net16;
+ wire net17;
+ wire net18;
+ wire net19;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24 = 1'b0;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net40;
+
+ assign io_out[0] = net9;
+ assign io_out[1] = net10;
+ assign io_out[2] = net11;
+ assign io_out[3] = net12;
+
+ not_cell gate7 (
+ .in (net4),
+ .out (net16)
+ );
+ dff_cell flipflop3 (
+ .d (net17),
+ .clk (net1),
+ .q (net12),
+ .notq (net18)
+ );
+ xor_cell gate8 (
+ .a (net2),
+ .b (net12),
+ .out (net19)
+ );
+ mux_cell mux2 (
+ .a (net19),
+ .b (net8),
+ .sel (net3),
+ .out (net17)
+ );
+ and_cell gate12 (
+ .a (net2),
+ .b (net20),
+ .out (net21)
+ );
+ or_cell gate10 (
+ .a (net22),
+ .b (net23),
+ .out (net20)
+ );
+ and_cell gate11 (
+ .a (net16),
+ .b (net12),
+ .out (net22)
+ );
+ and_cell gate13 (
+ .a (net4),
+ .b (net18),
+ .out (net23)
+ );
+ dff_cell flipflop2 (
+ .d (net25),
+ .clk (net1),
+ .q (net11),
+ .notq (net26)
+ );
+ xor_cell gate15 (
+ .a (net21),
+ .b (net11),
+ .out (net27)
+ );
+ mux_cell mux3 (
+ .a (net27),
+ .b (net7),
+ .sel (net3),
+ .out (net25)
+ );
+ and_cell gate16 (
+ .a (net21),
+ .b (net28),
+ .out (net29)
+ );
+ or_cell gate17 (
+ .a (net30),
+ .b (net31),
+ .out (net28)
+ );
+ and_cell gate18 (
+ .a (net22),
+ .b (net11),
+ .out (net30)
+ );
+ and_cell gate19 (
+ .a (net23),
+ .b (net26),
+ .out (net31)
+ );
+ dff_cell flipflop4 (
+ .d (net32),
+ .clk (net1),
+ .q (net10),
+ .notq (net33)
+ );
+ xor_cell gate14 (
+ .a (net29),
+ .b (net10),
+ .out (net34)
+ );
+ mux_cell mux4 (
+ .a (net34),
+ .b (net6),
+ .sel (net3),
+ .out (net32)
+ );
+ and_cell gate20 (
+ .a (net29),
+ .b (net35),
+ .out (net36)
+ );
+ or_cell gate21 (
+ .a (net37),
+ .b (net38),
+ .out (net35)
+ );
+ and_cell gate22 (
+ .a (net30),
+ .b (net10),
+ .out (net37)
+ );
+ and_cell gate23 (
+ .a (net31),
+ .b (net33),
+ .out (net38)
+ );
+ dff_cell flipflop5 (
+ .d (net39),
+ .clk (net1),
+ .q (net9)
+ );
+ xor_cell gate24 (
+ .a (net36),
+ .b (net9),
+ .out (net40)
+ );
+ mux_cell mux5 (
+ .a (net40),
+ .b (net5),
+ .sel (net3),
+ .out (net39)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_341571228858843732.v b/verilog/rtl/user_module_341571228858843732.v
new file mode 100644
index 0000000..24cbb44
--- /dev/null
+++ b/verilog/rtl/user_module_341571228858843732.v
@@ -0,0 +1,81 @@
+/* Automatically generated from https://wokwi.com/projects/341571228858843732 */
+
+`default_nettype none
+
+module user_module_341571228858843732(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[0];
+ wire net2 = io_in[1];
+ wire net3 = io_in[2];
+ wire net4 = io_in[3];
+ wire net5 = io_in[4];
+ wire net6 = io_in[5];
+ wire net7 = io_in[6];
+ wire net8 = io_in[7];
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15 = 1'b0;
+ wire net16 = 1'b1;
+ wire net17 = 1'b1;
+
+ assign io_out[0] = net1;
+ assign io_out[1] = net2;
+ assign io_out[2] = net9;
+ assign io_out[3] = net10;
+ assign io_out[4] = net11;
+ assign io_out[5] = net12;
+ assign io_out[6] = net13;
+ assign io_out[7] = net14;
+
+ or_cell gate2 (
+
+ );
+ xor_cell gate3 (
+
+ );
+ nand_cell gate4 (
+
+ );
+ buffer_cell gate6 (
+
+ );
+ mux_cell mux1 (
+
+ );
+ dff_cell flipflop1 (
+ .d (net3),
+ .clk (net1),
+ .q (net9)
+ );
+ dff_cell flipflop2 (
+ .d (net4),
+ .clk (net1),
+ .q (net10)
+ );
+ dff_cell flipflop3 (
+ .d (net5),
+ .clk (net1),
+ .q (net11)
+ );
+ dff_cell flipflop4 (
+ .d (net6),
+ .clk (net1),
+ .q (net12)
+ );
+ dff_cell flipflop5 (
+ .d (net7),
+ .clk (net1),
+ .q (net13)
+ );
+ dff_cell flipflop6 (
+ .d (net8),
+ .clk (net1),
+ .q (net14)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_341589685194195540.v b/verilog/rtl/user_module_341589685194195540.v
new file mode 100644
index 0000000..6ab4d55
--- /dev/null
+++ b/verilog/rtl/user_module_341589685194195540.v
@@ -0,0 +1,93 @@
+/* Automatically generated from https://wokwi.com/projects/341589685194195540 */
+
+`default_nettype none
+
+module user_module_341589685194195540(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[4];
+ wire net2 = io_in[5];
+ wire net3 = io_in[6];
+ wire net4 = io_in[7];
+ wire net5;
+ wire net6 = 1'b0;
+ wire net7 = 1'b1;
+ wire net8 = 1'b1;
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15;
+ wire net16;
+ wire net17;
+ wire net18;
+
+ assign io_out[7] = net5;
+
+ and_cell gate1 (
+ .a (net1),
+ .b (net9),
+ .out (net10)
+ );
+ or_cell gate2 (
+
+ );
+ xor_cell gate3 (
+ .a (net11),
+ .b (net12),
+ .out (net5)
+ );
+ nand_cell gate4 (
+
+ );
+ not_cell gate5 (
+ .in (net13),
+ .out (net14)
+ );
+ buffer_cell gate6 (
+ .in (net15),
+ .out (net9)
+ );
+ mux_cell mux1 (
+
+ );
+ dff_cell flipflop1 (
+
+ );
+ not_cell gate7 (
+
+ );
+ and_cell gate8 (
+ .a (net14),
+ .b (net3),
+ .out (net16)
+ );
+ xor_cell gate9 (
+ .a (net10),
+ .b (net16),
+ .out (net11)
+ );
+ buffer_cell gate10 (
+ .in (net2),
+ .out (net15)
+ );
+ buffer_cell gate11 (
+ .in (net2),
+ .out (net13)
+ );
+ buffer_cell gate12 (
+ .in (net17),
+ .out (net18)
+ );
+ buffer_cell gate13 (
+ .in (net18),
+ .out (net12)
+ );
+ buffer_cell gate14 (
+ .in (net4),
+ .out (net17)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_341608574336631379.v b/verilog/rtl/user_module_341608574336631379.v
new file mode 100644
index 0000000..289dc77
--- /dev/null
+++ b/verilog/rtl/user_module_341608574336631379.v
@@ -0,0 +1,194 @@
+/* Automatically generated from https://wokwi.com/projects/341608574336631379 */
+
+`default_nettype none
+
+module user_module_341608574336631379(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[0];
+ wire net2 = io_in[1];
+ wire net3 = io_in[2];
+ wire net4 = io_in[3];
+ wire net5 = io_in[4];
+ wire net6 = io_in[5];
+ wire net7 = io_in[6];
+ wire net8 = io_in[7];
+ wire net9;
+ wire net10;
+ wire net11 = 1'b0;
+ wire net12 = 1'b1;
+ wire net13 = 1'b1;
+ wire net14;
+ wire net15;
+ wire net16;
+ wire net17;
+ wire net18;
+ wire net19;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+
+ assign io_out[0] = net9;
+ assign io_out[1] = net10;
+
+ and_cell gate1 (
+ .a (net14),
+ .b (net8),
+ .out (net15)
+ );
+ or_cell gate2 (
+
+ );
+ xor_cell gate3 (
+ .a (net16),
+ .b (net15),
+ .out (net10)
+ );
+ nand_cell gate4 (
+
+ );
+ not_cell gate5 (
+
+ );
+ buffer_cell gate6 (
+
+ );
+ mux_cell mux1 (
+
+ );
+ dff_cell flipflop1 (
+
+ );
+ not_cell gate7 (
+ .in (net2),
+ .out (net17)
+ );
+ and_cell gate8 (
+ .a (net17),
+ .b (net18),
+ .out (net19)
+ );
+ and_cell gate9 (
+ .a (net20),
+ .b (net3),
+ .out (net21)
+ );
+ and_cell gate10 (
+ .a (net4),
+ .b (net22),
+ .out (net23)
+ );
+ xor_cell gate11 (
+ .a (net24),
+ .b (net19),
+ .out (net25)
+ );
+ xor_cell gate12 (
+ .a (net21),
+ .b (net23),
+ .out (net26)
+ );
+ xor_cell gate13 (
+ .a (net27),
+ .b (net26),
+ .out (net9)
+ );
+ xor_cell gate14 (
+ .a (net28),
+ .b (net29),
+ .out (net30)
+ );
+ and_cell gate15 (
+ .a (net31),
+ .b (net32),
+ .out (net29)
+ );
+ not_cell gate16 (
+ .in (net5),
+ .out (net32)
+ );
+ and_cell gate17 (
+ .a (net3),
+ .b (net7),
+ .out (net33)
+ );
+ xor_cell gate18 (
+ .a (net30),
+ .b (net34),
+ .out (net16)
+ );
+ buffer_cell gate19 (
+ .in (net4),
+ .out (net18)
+ );
+ buffer_cell gate20 (
+ .in (net25),
+ .out (net27)
+ );
+ buffer_cell gate21 (
+ .in (net2),
+ .out (net35)
+ );
+ buffer_cell gate22 (
+ .in (net35),
+ .out (net20)
+ );
+ buffer_cell gate23 (
+ .in (net36),
+ .out (net22)
+ );
+ buffer_cell gate24 (
+ .in (net5),
+ .out (net36)
+ );
+ buffer_cell gate25 (
+ .in (net22),
+ .out (net14)
+ );
+ buffer_cell gate26 (
+ .in (net3),
+ .out (net31)
+ );
+ buffer_cell gate27 (
+ .in (net37),
+ .out (net34)
+ );
+ buffer_cell gate28 (
+ .in (net33),
+ .out (net37)
+ );
+ buffer_cell gate29 (
+ .in (net6),
+ .out (net38)
+ );
+ buffer_cell gate30 (
+ .in (net38),
+ .out (net28)
+ );
+ buffer_cell gate31 (
+ .in (net39),
+ .out (net24)
+ );
+ buffer_cell gate32 (
+ .in (net1),
+ .out (net39)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_348381622440034899.v b/verilog/rtl/user_module_348381622440034899.v
new file mode 100644
index 0000000..e567135
--- /dev/null
+++ b/verilog/rtl/user_module_348381622440034899.v
@@ -0,0 +1,894 @@
+/* Automatically generated from https://wokwi.com/projects/348381622440034899 */
+
+`default_nettype none
+
+module user_module_348381622440034899(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[0];
+ wire net2 = io_in[1];
+ wire net3 = io_in[2];
+ wire net4 = io_in[3];
+ wire net5 = io_in[4];
+ wire net6;
+ wire net7;
+ wire net8;
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13 = 1'b0;
+ wire net14 = 1'b1;
+ wire net15 = 1'b1;
+ wire net16;
+ wire net17;
+ wire net18;
+ wire net19;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
+ wire net49;
+ wire net50;
+ wire net51;
+ wire net52;
+ wire net53;
+ wire net54;
+ wire net55;
+ wire net56;
+ wire net57;
+ wire net58;
+ wire net59;
+ wire net60;
+ wire net61;
+ wire net62;
+ wire net63;
+ wire net64;
+ wire net65;
+ wire net66;
+ wire net67;
+ wire net68;
+ wire net69;
+ wire net70;
+ wire net71;
+ wire net72;
+ wire net73;
+ wire net74;
+ wire net75;
+ wire net76;
+ wire net77;
+ wire net78;
+ wire net79;
+ wire net80;
+ wire net81;
+ wire net82;
+ wire net83;
+ wire net84;
+ wire net85;
+ wire net86;
+ wire net87;
+ wire net88;
+ wire net89;
+ wire net90;
+ wire net91;
+ wire net92;
+ wire net93;
+ wire net94;
+ wire net95;
+ wire net96;
+ wire net97;
+ wire net98;
+ wire net99;
+ wire net100;
+ wire net101;
+ wire net102;
+ wire net103;
+ wire net104;
+ wire net105;
+ wire net106;
+ wire net107;
+ wire net108;
+ wire net109;
+ wire net110;
+ wire net111;
+ wire net112;
+ wire net113;
+ wire net114;
+ wire net115;
+ wire net116;
+ wire net117;
+ wire net118;
+ wire net119;
+ wire net120;
+ wire net121;
+ wire net122;
+ wire net123;
+ wire net124;
+ wire net125;
+ wire net126;
+ wire net127;
+ wire net128;
+ wire net129;
+ wire net130;
+ wire net131;
+ wire net132;
+ wire net133;
+ wire net134;
+ wire net135;
+ wire net136;
+ wire net137;
+ wire net138;
+ wire net139;
+ wire net140;
+ wire net141;
+ wire net142;
+ wire net143;
+ wire net144;
+ wire net145;
+ wire net146;
+ wire net147;
+ wire net148;
+ wire net149;
+ wire net150;
+ wire net151;
+ wire net152;
+ wire net153;
+ wire net154;
+ wire net155;
+
+ assign io_out[0] = net6;
+ assign io_out[1] = net7;
+ assign io_out[2] = net8;
+ assign io_out[3] = net9;
+ assign io_out[4] = net10;
+ assign io_out[5] = net11;
+ assign io_out[6] = net12;
+
+ dff_cell flipflop2 (
+ .d (net16),
+ .clk (net1),
+ .q (net17),
+ .notq (net16)
+ );
+ dff_cell flipflop3 (
+ .d (net18),
+ .clk (net1),
+ .q (net19)
+ );
+ xor_cell gate7 (
+ .a (net19),
+ .b (net17),
+ .out (net18)
+ );
+ and_cell gate8 (
+ .a (net19),
+ .b (net17),
+ .out (net20)
+ );
+ dff_cell flipflop4 (
+ .d (net21),
+ .clk (net1),
+ .q (net22)
+ );
+ and_cell gate9 (
+ .a (net22),
+ .b (net20),
+ .out (net23)
+ );
+ xor_cell gate10 (
+ .a (net22),
+ .b (net20),
+ .out (net21)
+ );
+ dff_cell flipflop5 (
+ .d (net24),
+ .clk (net1),
+ .q (net25)
+ );
+ xor_cell gate11 (
+ .a (net25),
+ .b (net23),
+ .out (net24)
+ );
+ dff_cell flipflop6 (
+ .d (net26),
+ .clk (net27),
+ .q (net28)
+ );
+ dff_cell flipflop7 (
+ .d (net29),
+ .clk (net27),
+ .q (net30)
+ );
+ dff_cell flipflop8 (
+ .d (net30),
+ .clk (net27),
+ .q (net31)
+ );
+ or_cell gate12 (
+ .a (net28),
+ .b (net30),
+ .out (net32)
+ );
+ or_cell gate13 (
+ .a (net32),
+ .b (net33),
+ .out (net6)
+ );
+ dff_cell flipflop9 (
+ .d (net34),
+ .clk (net27),
+ .q (net35)
+ );
+ dff_cell flipflop10 (
+ .d (net36),
+ .clk (net27),
+ .q (net37)
+ );
+ dff_cell flipflop11 (
+ .d (net37),
+ .clk (net27),
+ .q (net38)
+ );
+ or_cell gate14 (
+ .a (net35),
+ .b (net37),
+ .out (net39)
+ );
+ or_cell gate15 (
+ .a (net39),
+ .b (net40),
+ .out (net7)
+ );
+ dff_cell flipflop12 (
+ .d (net41),
+ .clk (net27),
+ .q (net42)
+ );
+ dff_cell flipflop13 (
+ .d (net43),
+ .clk (net27),
+ .q (net44)
+ );
+ dff_cell flipflop14 (
+ .d (net44),
+ .clk (net27),
+ .q (net45)
+ );
+ or_cell gate16 (
+ .a (net42),
+ .b (net44),
+ .out (net46)
+ );
+ or_cell gate17 (
+ .a (net46),
+ .b (net47),
+ .out (net8)
+ );
+ dff_cell flipflop15 (
+ .d (net48),
+ .clk (net27),
+ .q (net49)
+ );
+ dff_cell flipflop16 (
+ .d (net50),
+ .clk (net27),
+ .q (net51)
+ );
+ dff_cell flipflop17 (
+ .d (net51),
+ .clk (net27),
+ .q (net52)
+ );
+ or_cell gate18 (
+ .a (net49),
+ .b (net51),
+ .out (net53)
+ );
+ or_cell gate19 (
+ .a (net53),
+ .b (net54),
+ .out (net9)
+ );
+ dff_cell flipflop18 (
+ .d (net55),
+ .clk (net27),
+ .q (net56)
+ );
+ dff_cell flipflop19 (
+ .d (net57),
+ .clk (net27),
+ .q (net58)
+ );
+ dff_cell flipflop20 (
+ .d (net58),
+ .clk (net27),
+ .q (net59)
+ );
+ or_cell gate20 (
+ .a (net56),
+ .b (net58),
+ .out (net60)
+ );
+ or_cell gate21 (
+ .a (net60),
+ .b (net61),
+ .out (net10)
+ );
+ dff_cell flipflop21 (
+ .d (net62),
+ .clk (net27),
+ .q (net63)
+ );
+ dff_cell flipflop22 (
+ .d (net64),
+ .clk (net27),
+ .q (net65)
+ );
+ dff_cell flipflop23 (
+ .d (net65),
+ .clk (net27),
+ .q (net66)
+ );
+ or_cell gate22 (
+ .a (net63),
+ .b (net65),
+ .out (net67)
+ );
+ or_cell gate23 (
+ .a (net67),
+ .b (net68),
+ .out (net11)
+ );
+ dff_cell flipflop24 (
+ .d (net69),
+ .clk (net27),
+ .q (net70)
+ );
+ dff_cell flipflop25 (
+ .d (net71),
+ .clk (net27),
+ .q (net72)
+ );
+ dff_cell flipflop26 (
+ .d (net72),
+ .clk (net27),
+ .q (net73)
+ );
+ or_cell gate24 (
+ .a (net70),
+ .b (net72),
+ .out (net74)
+ );
+ or_cell gate25 (
+ .a (net74),
+ .b (net75),
+ .out (net12)
+ );
+ dff_cell flipflop27 (
+ .d (net76),
+ .clk (net27),
+ .q (net77)
+ );
+ dff_cell flipflop28 (
+ .d (net78),
+ .clk (net27),
+ .q (net79)
+ );
+ dff_cell flipflop29 (
+ .d (net79),
+ .clk (net27),
+ .q (net80)
+ );
+ dff_cell flipflop30 (
+ .d (net81),
+ .clk (net27),
+ .q (net76),
+ .notq (net82)
+ );
+ or_cell gate1 (
+ .a (net83),
+ .b (net84),
+ .out (net26)
+ );
+ not_cell not1 (
+ .in (net83),
+ .out (net85)
+ );
+ and_cell gate2 (
+ .a (net85),
+ .b (net86),
+ .out (net34)
+ );
+ and_cell gate3 (
+ .a (net85),
+ .b (net87),
+ .out (net41)
+ );
+ and_cell gate4 (
+ .a (net85),
+ .b (net88),
+ .out (net48)
+ );
+ and_cell gate5 (
+ .a (net85),
+ .b (net89),
+ .out (net55)
+ );
+ and_cell gate6 (
+ .a (net85),
+ .b (net90),
+ .out (net62)
+ );
+ and_cell gate26 (
+ .a (net85),
+ .b (net91),
+ .out (net69)
+ );
+ or_cell gate28 (
+ .a (net77),
+ .b (net83),
+ .out (net78)
+ );
+ xor_cell gate27 (
+ .a (net76),
+ .b (net80),
+ .out (net81)
+ );
+ and_cell gate29 (
+ .a (net28),
+ .b (net85),
+ .out (net29)
+ );
+ or_cell gate30 (
+ .a (net83),
+ .b (net35),
+ .out (net36)
+ );
+ and_cell gate31 (
+ .a (net42),
+ .b (net85),
+ .out (net43)
+ );
+ and_cell gate32 (
+ .a (net49),
+ .b (net85),
+ .out (net50)
+ );
+ and_cell gate33 (
+ .a (net56),
+ .b (net85),
+ .out (net57)
+ );
+ and_cell gate34 (
+ .a (net63),
+ .b (net85),
+ .out (net64)
+ );
+ and_cell gate35 (
+ .a (net70),
+ .b (net85),
+ .out (net71)
+ );
+ or_cell gate36 (
+ .a (net92),
+ .b (net93),
+ .out (net84)
+ );
+ and_cell gate37 (
+ .a (net35),
+ .b (net94),
+ .out (net92)
+ );
+ and_cell gate38 (
+ .a (net63),
+ .b (net95),
+ .out (net93)
+ );
+ or_cell gate39 (
+ .a (net44),
+ .b (net72),
+ .out (net94)
+ );
+ or_cell gate40 (
+ .a (net58),
+ .b (net72),
+ .out (net95)
+ );
+ and_cell gate41 (
+ .a (net96),
+ .b (net76),
+ .out (net91)
+ );
+ or_cell gate42 (
+ .a (net97),
+ .b (net98),
+ .out (net99)
+ );
+ or_cell gate43 (
+ .a (net100),
+ .b (net101),
+ .out (net102)
+ );
+ or_cell gate44 (
+ .a (net99),
+ .b (net102),
+ .out (net96)
+ );
+ and_cell gate45 (
+ .a (net30),
+ .b (net35),
+ .out (net97)
+ );
+ and_cell gate46 (
+ .a (net51),
+ .b (net42),
+ .out (net98)
+ );
+ and_cell gate47 (
+ .a (net51),
+ .b (net56),
+ .out (net100)
+ );
+ and_cell gate48 (
+ .a (net30),
+ .b (net63),
+ .out (net101)
+ );
+ or_cell gate49 (
+ .a (net103),
+ .b (net104),
+ .out (net88)
+ );
+ and_cell gate50 (
+ .a (net42),
+ .b (net105),
+ .out (net103)
+ );
+ and_cell gate51 (
+ .a (net56),
+ .b (net106),
+ .out (net104)
+ );
+ or_cell gate52 (
+ .a (net37),
+ .b (net72),
+ .out (net105)
+ );
+ or_cell gate53 (
+ .a (net65),
+ .b (net72),
+ .out (net106)
+ );
+ or_cell gate54 (
+ .a (net107),
+ .b (net108),
+ .out (net86)
+ );
+ and_cell gate55 (
+ .a (net109),
+ .b (net82),
+ .out (net108)
+ );
+ or_cell gate56 (
+ .a (net110),
+ .b (net111),
+ .out (net109)
+ );
+ and_cell gate57 (
+ .a (net112),
+ .b (net70),
+ .out (net110)
+ );
+ and_cell gate58 (
+ .a (net51),
+ .b (net42),
+ .out (net111)
+ );
+ and_cell gate59 (
+ .a (net28),
+ .b (net65),
+ .out (net107)
+ );
+ or_cell gate60 (
+ .a (net65),
+ .b (net58),
+ .out (net112)
+ );
+ or_cell gate61 (
+ .a (net113),
+ .b (net114),
+ .out (net89)
+ );
+ and_cell gate62 (
+ .a (net115),
+ .b (net82),
+ .out (net114)
+ );
+ or_cell gate63 (
+ .a (net116),
+ .b (net117),
+ .out (net115)
+ );
+ and_cell gate64 (
+ .a (net118),
+ .b (net70),
+ .out (net116)
+ );
+ and_cell gate65 (
+ .a (net30),
+ .b (net63),
+ .out (net117)
+ );
+ and_cell gate66 (
+ .a (net49),
+ .b (net44),
+ .out (net113)
+ );
+ or_cell gate67 (
+ .a (net44),
+ .b (net37),
+ .out (net118)
+ );
+ or_cell gate68 (
+ .a (net119),
+ .b (net120),
+ .out (net87)
+ );
+ and_cell gate69 (
+ .a (net58),
+ .b (net49),
+ .out (net119)
+ );
+ or_cell gate70 (
+ .a (net121),
+ .b (net122),
+ .out (net120)
+ );
+ and_cell gate71 (
+ .a (net123),
+ .b (net82),
+ .out (net121)
+ );
+ and_cell gate72 (
+ .a (net35),
+ .b (net30),
+ .out (net123)
+ );
+ and_cell gate73 (
+ .a (net124),
+ .b (net76),
+ .out (net122)
+ );
+ or_cell gate74 (
+ .a (net65),
+ .b (net58),
+ .out (net125)
+ );
+ and_cell gate75 (
+ .a (net70),
+ .b (net125),
+ .out (net124)
+ );
+ or_cell gate76 (
+ .a (net126),
+ .b (net127),
+ .out (net90)
+ );
+ and_cell gate77 (
+ .a (net28),
+ .b (net37),
+ .out (net126)
+ );
+ or_cell gate78 (
+ .a (net128),
+ .b (net129),
+ .out (net127)
+ );
+ and_cell gate79 (
+ .a (net130),
+ .b (net82),
+ .out (net128)
+ );
+ and_cell gate80 (
+ .a (net131),
+ .b (net76),
+ .out (net129)
+ );
+ and_cell gate81 (
+ .a (net56),
+ .b (net51),
+ .out (net130)
+ );
+ and_cell gate82 (
+ .a (net118),
+ .b (net70),
+ .out (net131)
+ );
+ mux_cell mux1 (
+ .a (net25),
+ .b (net1),
+ .sel (net4),
+ .out (net27)
+ );
+ xor_cell gate83 (
+ .a (net86),
+ .b (net87),
+ .out (net132)
+ );
+ xor_cell gate84 (
+ .a (net88),
+ .b (net89),
+ .out (net133)
+ );
+ xor_cell gate85 (
+ .a (net90),
+ .b (net91),
+ .out (net134)
+ );
+ and_cell gate86 (
+ .a (net84),
+ .b (net135),
+ .out (net136)
+ );
+ and_cell gate87 (
+ .a (net137),
+ .b (net132),
+ .out (net138)
+ );
+ and_cell gate88 (
+ .a (net133),
+ .b (net139),
+ .out (net140)
+ );
+ and_cell gate89 (
+ .a (net141),
+ .b (net134),
+ .out (net142)
+ );
+ not_cell gate90 (
+ .in (net84),
+ .out (net137)
+ );
+ or_cell gate91 (
+ .a (net86),
+ .b (net87),
+ .out (net143)
+ );
+ not_cell gate92 (
+ .in (net143),
+ .out (net135)
+ );
+ or_cell gate93 (
+ .a (net88),
+ .b (net89),
+ .out (net144)
+ );
+ not_cell gate94 (
+ .in (net144),
+ .out (net141)
+ );
+ or_cell gate95 (
+ .a (net90),
+ .b (net91),
+ .out (net145)
+ );
+ not_cell gate96 (
+ .in (net145),
+ .out (net139)
+ );
+ and_cell gate97 (
+ .a (net141),
+ .b (net139),
+ .out (net146)
+ );
+ and_cell gate98 (
+ .a (net137),
+ .b (net135),
+ .out (net147)
+ );
+ and_cell gate99 (
+ .a (net148),
+ .b (net146),
+ .out (net149)
+ );
+ and_cell gate100 (
+ .a (net147),
+ .b (net150),
+ .out (net151)
+ );
+ or_cell gate101 (
+ .a (net149),
+ .b (net151),
+ .out (net152)
+ );
+ or_cell gate102 (
+ .a (net136),
+ .b (net138),
+ .out (net148)
+ );
+ or_cell gate103 (
+ .a (net140),
+ .b (net142),
+ .out (net150)
+ );
+ not_cell gate104 (
+ .in (net152),
+ .out (net153)
+ );
+ or_cell gate105 (
+ .a (net154),
+ .b (net3),
+ .out (net83)
+ );
+ and_cell gate106 (
+ .a (net153),
+ .b (net155),
+ .out (net154)
+ );
+ not_cell not2 (
+ .in (net2),
+ .out (net155)
+ );
+ and_cell gate107 (
+ .a (net31),
+ .b (net5),
+ .out (net33)
+ );
+ and_cell gate108 (
+ .a (net38),
+ .b (net5),
+ .out (net40)
+ );
+ and_cell gate109 (
+ .a (net45),
+ .b (net5),
+ .out (net47)
+ );
+ and_cell gate110 (
+ .a (net52),
+ .b (net5),
+ .out (net54)
+ );
+ and_cell gate111 (
+ .a (net59),
+ .b (net5),
+ .out (net61)
+ );
+ and_cell gate112 (
+ .a (net66),
+ .b (net5),
+ .out (net68)
+ );
+ and_cell gate113 (
+ .a (net73),
+ .b (net5),
+ .out (net75)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_348787952842703444.v b/verilog/rtl/user_module_348787952842703444.v
new file mode 100644
index 0000000..42d5121
--- /dev/null
+++ b/verilog/rtl/user_module_348787952842703444.v
@@ -0,0 +1,244 @@
+/* Automatically generated from https://wokwi.com/projects/348787952842703444 */
+
+`default_nettype none
+
+module user_module_348787952842703444(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[0];
+ wire net2 = io_in[1];
+ wire net3 = io_in[2];
+ wire net4 = io_in[3];
+ wire net5 = io_in[4];
+ wire net6 = io_in[5];
+ wire net7 = io_in[6];
+ wire net8 = io_in[7];
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14 = 1'b0;
+ wire net15 = 1'b1;
+ wire net16 = 1'b1;
+ wire net17;
+ wire net18;
+ wire net19;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34 = 1'b0;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
+
+ assign io_out[0] = net9;
+ assign io_out[1] = net10;
+ assign io_out[2] = net11;
+ assign io_out[3] = net12;
+ assign io_out[4] = net13;
+
+ xor_cell gate3 (
+ .a (net17),
+ .b (net18),
+ .out (net19)
+ );
+ nand_cell gate4 (
+ .a (net1),
+ .b (net6),
+ .out (net17)
+ );
+ nand_cell gate1 (
+ .a (net1),
+ .b (net5),
+ .out (net20)
+ );
+ nand_cell gate7 (
+ .a (net2),
+ .b (net5),
+ .out (net18)
+ );
+ nand_cell gate8 (
+ .a (net2),
+ .b (net6),
+ .out (net21)
+ );
+ nand_cell gate9 (
+ .a (net17),
+ .b (net18),
+ .out (net22)
+ );
+ nand_cell gate10 (
+ .a (net22),
+ .b (net21),
+ .out (net23)
+ );
+ xor_cell gate11 (
+ .a (net22),
+ .b (net21),
+ .out (net24)
+ );
+ xor_cell gate2 (
+ .a (net25),
+ .b (net26),
+ .out (net27)
+ );
+ nand_cell gate5 (
+ .a (net3),
+ .b (net8),
+ .out (net25)
+ );
+ nand_cell gate6 (
+ .a (net3),
+ .b (net7),
+ .out (net28)
+ );
+ nand_cell gate12 (
+ .a (net4),
+ .b (net7),
+ .out (net26)
+ );
+ nand_cell gate13 (
+ .a (net4),
+ .b (net8),
+ .out (net29)
+ );
+ nand_cell gate14 (
+ .a (net25),
+ .b (net26),
+ .out (net30)
+ );
+ nand_cell gate15 (
+ .a (net30),
+ .b (net29),
+ .out (net31)
+ );
+ xor_cell gate16 (
+ .a (net30),
+ .b (net29),
+ .out (net32)
+ );
+ xor_cell xor1 (
+ .a (net20),
+ .b (net28),
+ .out (net33)
+ );
+ xor_cell xor2 (
+ .a (net33),
+ .b (net34),
+ .out (net9)
+ );
+ nand_cell gate17 (
+ .a (net34),
+ .b (net33),
+ .out (net35)
+ );
+ nand_cell gate18 (
+ .a (net28),
+ .b (net20),
+ .out (net36)
+ );
+ or_cell or1 (
+ .a (net35),
+ .b (net36),
+ .out (net37)
+ );
+ xor_cell xor3 (
+ .a (net19),
+ .b (net27),
+ .out (net38)
+ );
+ xor_cell xor4 (
+ .a (net38),
+ .b (net37),
+ .out (net10)
+ );
+ nand_cell gate19 (
+ .a (net37),
+ .b (net38),
+ .out (net39)
+ );
+ nand_cell gate20 (
+ .a (net27),
+ .b (net19),
+ .out (net40)
+ );
+ or_cell or2 (
+ .a (net39),
+ .b (net40),
+ .out (net41)
+ );
+ xor_cell xor5 (
+ .a (net24),
+ .b (net32),
+ .out (net42)
+ );
+ xor_cell xor6 (
+ .a (net42),
+ .b (net41),
+ .out (net11)
+ );
+ nand_cell gate21 (
+ .a (net41),
+ .b (net42),
+ .out (net43)
+ );
+ nand_cell gate22 (
+ .a (net32),
+ .b (net24),
+ .out (net44)
+ );
+ or_cell or3 (
+ .a (net43),
+ .b (net44),
+ .out (net45)
+ );
+ xor_cell xor7 (
+ .a (net23),
+ .b (net31),
+ .out (net46)
+ );
+ xor_cell xor8 (
+ .a (net46),
+ .b (net45),
+ .out (net12)
+ );
+ nand_cell gate23 (
+ .a (net45),
+ .b (net46),
+ .out (net47)
+ );
+ nand_cell gate24 (
+ .a (net31),
+ .b (net23),
+ .out (net48)
+ );
+ or_cell or4 (
+ .a (net47),
+ .b (net48),
+ .out (net13)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_349405063877231188.v b/verilog/rtl/user_module_349405063877231188.v
new file mode 100644
index 0000000..adae01e
--- /dev/null
+++ b/verilog/rtl/user_module_349405063877231188.v
@@ -0,0 +1,1430 @@
+/* Automatically generated from https://wokwi.com/projects/349405063877231188 */
+
+`default_nettype none
+
+module user_module_349405063877231188(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[3];
+ wire net2 = io_in[4];
+ wire net3 = io_in[5];
+ wire net4 = io_in[6];
+ wire net5 = io_in[7];
+ wire net6 = 1'b1;
+ wire net7 = 1'b1;
+ wire net8 = 1'b1;
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15;
+ wire net16;
+ wire net17;
+ wire net18;
+ wire net19;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
+ wire net49;
+ wire net50;
+ wire net51;
+ wire net52;
+ wire net53;
+ wire net54;
+ wire net55;
+ wire net56;
+ wire net57;
+ wire net58;
+ wire net59;
+ wire net60;
+ wire net61;
+ wire net62;
+ wire net63;
+ wire net64;
+ wire net65;
+ wire net66;
+ wire net67;
+ wire net68;
+ wire net69;
+ wire net70;
+ wire net71;
+ wire net72;
+ wire net73;
+ wire net74;
+ wire net75;
+ wire net76;
+ wire net77;
+ wire net78;
+ wire net79;
+ wire net80;
+ wire net81 = 1'b1;
+ wire net82;
+ wire net83;
+ wire net84;
+ wire net85;
+ wire net86;
+ wire net87;
+ wire net88;
+ wire net89;
+ wire net90;
+ wire net91;
+ wire net92;
+ wire net93;
+ wire net94;
+ wire net95;
+ wire net96;
+ wire net97;
+ wire net98;
+ wire net99;
+ wire net100;
+ wire net101;
+ wire net102;
+ wire net103;
+ wire net104;
+ wire net105;
+ wire net106;
+ wire net107;
+ wire net108;
+ wire net109;
+ wire net110;
+ wire net111;
+ wire net112;
+ wire net113;
+ wire net114;
+ wire net115;
+ wire net116;
+ wire net117;
+ wire net118;
+ wire net119;
+ wire net120;
+ wire net121;
+ wire net122;
+ wire net123;
+ wire net124;
+ wire net125;
+ wire net126;
+ wire net127;
+ wire net128;
+ wire net129;
+ wire net130;
+ wire net131;
+ wire net132;
+ wire net133;
+ wire net134;
+ wire net135;
+ wire net136;
+ wire net137;
+ wire net138;
+ wire net139;
+ wire net140;
+ wire net141;
+ wire net142;
+ wire net143;
+ wire net144;
+ wire net145;
+ wire net146;
+ wire net147;
+ wire net148;
+ wire net149;
+ wire net150;
+ wire net151;
+ wire net152 = 1'b1;
+ wire net153;
+ wire net154;
+ wire net155;
+ wire net156;
+ wire net157;
+ wire net158;
+ wire net159;
+ wire net160;
+ wire net161;
+ wire net162;
+ wire net163;
+ wire net164;
+ wire net165;
+ wire net166;
+ wire net167;
+ wire net168;
+ wire net169;
+ wire net170;
+ wire net171;
+ wire net172;
+ wire net173;
+ wire net174;
+ wire net175;
+ wire net176;
+ wire net177;
+ wire net178;
+ wire net179;
+ wire net180;
+ wire net181;
+ wire net182;
+ wire net183;
+ wire net184;
+ wire net185;
+ wire net186;
+ wire net187;
+ wire net188;
+ wire net189;
+ wire net190;
+ wire net191;
+ wire net192;
+ wire net193;
+ wire net194;
+ wire net195;
+ wire net196;
+ wire net197;
+ wire net198;
+ wire net199;
+ wire net200;
+ wire net201;
+ wire net202;
+ wire net203;
+ wire net204;
+ wire net205;
+ wire net206;
+ wire net207;
+ wire net208;
+ wire net209;
+ wire net210;
+ wire net211;
+ wire net212;
+ wire net213;
+ wire net214;
+ wire net215;
+ wire net216;
+ wire net217;
+ wire net218;
+ wire net219;
+ wire net220;
+ wire net221;
+ wire net222;
+ wire net223;
+ wire net224;
+ wire net225;
+ wire net226;
+ wire net227;
+ wire net228;
+ wire net229;
+ wire net230;
+ wire net231;
+ wire net232;
+ wire net233;
+ wire net234 = 1'b0;
+ wire net235;
+ wire net236;
+ wire net237;
+ wire net238;
+ wire net239;
+ wire net240;
+ wire net241;
+ wire net242;
+ wire net243;
+ wire net244;
+ wire net245;
+ wire net246;
+ wire net247;
+ wire net248;
+ wire net249;
+ wire net250;
+ wire net251;
+ wire net252;
+ wire net253;
+ wire net254;
+ wire net255;
+
+ and_cell gate1 (
+
+ );
+ or_cell gate2 (
+
+ );
+ xor_cell gate3 (
+
+ );
+ nand_cell gate4 (
+
+ );
+ not_cell gate5 (
+
+ );
+ buffer_cell gate6 (
+
+ );
+ mux_cell mux1 (
+
+ );
+ dff_cell flipflop1 (
+
+ );
+ dff_cell flipflop2 (
+ .d (net9),
+ .clk (net10),
+ .q (net11),
+ .notq (net12)
+ );
+ and_cell gate7 (
+ .a (net12),
+ .b (net8),
+ .out (net13)
+ );
+ and_cell gate8 (
+ .a (net14),
+ .b (net11),
+ .out (net15)
+ );
+ or_cell gate9 (
+ .a (net13),
+ .b (net15),
+ .out (net9)
+ );
+ not_cell gate10 (
+ .in (net8),
+ .out (net14)
+ );
+ dff_cell flipflop3 (
+ .d (net16),
+ .clk (net10),
+ .q (net17),
+ .notq (net18)
+ );
+ and_cell gate11 (
+ .a (net18),
+ .b (net19),
+ .out (net20)
+ );
+ and_cell gate12 (
+ .a (net21),
+ .b (net17),
+ .out (net22)
+ );
+ or_cell gate13 (
+ .a (net20),
+ .b (net22),
+ .out (net16)
+ );
+ not_cell gate14 (
+ .in (net19),
+ .out (net21)
+ );
+ and_cell gate15 (
+ .a (net23),
+ .b (net11),
+ .out (net24)
+ );
+ and_cell gate16 (
+ .a (net5),
+ .b (net12),
+ .out (net25)
+ );
+ or_cell gate17 (
+ .a (net24),
+ .b (net25),
+ .out (net19)
+ );
+ not_cell gate18 (
+ .in (net5),
+ .out (net23)
+ );
+ dff_cell flipflop4 (
+ .d (net26),
+ .clk (net10),
+ .q (net27),
+ .notq (net28)
+ );
+ and_cell gate19 (
+ .a (net28),
+ .b (net29),
+ .out (net30)
+ );
+ and_cell gate20 (
+ .a (net31),
+ .b (net27),
+ .out (net32)
+ );
+ or_cell gate21 (
+ .a (net30),
+ .b (net32),
+ .out (net26)
+ );
+ not_cell gate22 (
+ .in (net29),
+ .out (net31)
+ );
+ and_cell gate23 (
+ .a (net24),
+ .b (net17),
+ .out (net33)
+ );
+ and_cell gate24 (
+ .a (net18),
+ .b (net25),
+ .out (net34)
+ );
+ or_cell gate25 (
+ .a (net33),
+ .b (net34),
+ .out (net29)
+ );
+ dff_cell flipflop5 (
+ .d (net35),
+ .clk (net10),
+ .q (net36),
+ .notq (net37)
+ );
+ and_cell gate26 (
+ .a (net37),
+ .b (net38),
+ .out (net39)
+ );
+ and_cell gate27 (
+ .a (net40),
+ .b (net36),
+ .out (net41)
+ );
+ or_cell gate28 (
+ .a (net39),
+ .b (net41),
+ .out (net35)
+ );
+ not_cell gate29 (
+ .in (net38),
+ .out (net40)
+ );
+ and_cell gate30 (
+ .a (net33),
+ .b (net27),
+ .out (net42)
+ );
+ and_cell gate31 (
+ .a (net28),
+ .b (net34),
+ .out (net43)
+ );
+ or_cell gate32 (
+ .a (net42),
+ .b (net43),
+ .out (net38)
+ );
+ dff_cell flipflop6 (
+ .d (net44),
+ .clk (net10),
+ .q (net45),
+ .notq (net46)
+ );
+ and_cell gate33 (
+ .a (net46),
+ .b (net47),
+ .out (net48)
+ );
+ and_cell gate34 (
+ .a (net49),
+ .b (net45),
+ .out (net50)
+ );
+ or_cell gate35 (
+ .a (net48),
+ .b (net50),
+ .out (net44)
+ );
+ not_cell gate36 (
+ .in (net47),
+ .out (net49)
+ );
+ and_cell gate37 (
+ .a (net42),
+ .b (net36),
+ .out (net51)
+ );
+ and_cell gate38 (
+ .a (net37),
+ .b (net43),
+ .out (net52)
+ );
+ or_cell gate39 (
+ .a (net51),
+ .b (net52),
+ .out (net47)
+ );
+ dff_cell flipflop7 (
+ .d (net53),
+ .clk (net10),
+ .q (net54),
+ .notq (net55)
+ );
+ and_cell gate40 (
+ .a (net55),
+ .b (net56),
+ .out (net57)
+ );
+ and_cell gate41 (
+ .a (net58),
+ .b (net54),
+ .out (net59)
+ );
+ or_cell gate42 (
+ .a (net57),
+ .b (net59),
+ .out (net53)
+ );
+ not_cell gate43 (
+ .in (net56),
+ .out (net58)
+ );
+ and_cell gate44 (
+ .a (net51),
+ .b (net45),
+ .out (net60)
+ );
+ and_cell gate45 (
+ .a (net46),
+ .b (net52),
+ .out (net61)
+ );
+ or_cell gate46 (
+ .a (net60),
+ .b (net61),
+ .out (net56)
+ );
+ dff_cell flipflop8 (
+ .d (net62),
+ .clk (net10),
+ .q (net63),
+ .notq (net64)
+ );
+ and_cell gate47 (
+ .a (net64),
+ .b (net65),
+ .out (net66)
+ );
+ and_cell gate48 (
+ .a (net67),
+ .b (net63),
+ .out (net68)
+ );
+ or_cell gate49 (
+ .a (net66),
+ .b (net68),
+ .out (net62)
+ );
+ not_cell gate50 (
+ .in (net65),
+ .out (net67)
+ );
+ and_cell gate51 (
+ .a (net60),
+ .b (net54),
+ .out (net69)
+ );
+ and_cell gate52 (
+ .a (net55),
+ .b (net61),
+ .out (net70)
+ );
+ or_cell gate53 (
+ .a (net69),
+ .b (net70),
+ .out (net65)
+ );
+ dff_cell flipflop9 (
+ .d (net71),
+ .clk (net10),
+ .q (net72),
+ .notq (net73)
+ );
+ and_cell gate54 (
+ .a (net73),
+ .b (net74),
+ .out (net75)
+ );
+ and_cell gate55 (
+ .a (net76),
+ .b (net72),
+ .out (net77)
+ );
+ or_cell gate56 (
+ .a (net75),
+ .b (net77),
+ .out (net71)
+ );
+ not_cell gate57 (
+ .in (net74),
+ .out (net76)
+ );
+ and_cell gate58 (
+ .a (net69),
+ .b (net63),
+ .out (net78)
+ );
+ and_cell gate59 (
+ .a (net64),
+ .b (net70),
+ .out (net79)
+ );
+ or_cell gate60 (
+ .a (net78),
+ .b (net79),
+ .out (net74)
+ );
+ not_cell gate114 (
+ .in (net5),
+ .out (net80)
+ );
+ dff_cell flipflop10 (
+ .d (net82),
+ .clk (net83),
+ .q (net84),
+ .notq (net85)
+ );
+ and_cell gate61 (
+ .a (net85),
+ .b (net81),
+ .out (net86)
+ );
+ and_cell gate62 (
+ .a (net87),
+ .b (net84),
+ .out (net88)
+ );
+ or_cell gate63 (
+ .a (net86),
+ .b (net88),
+ .out (net82)
+ );
+ not_cell gate64 (
+ .in (net81),
+ .out (net87)
+ );
+ dff_cell flipflop11 (
+ .d (net89),
+ .clk (net83),
+ .q (net90),
+ .notq (net91)
+ );
+ and_cell gate65 (
+ .a (net91),
+ .b (net92),
+ .out (net93)
+ );
+ and_cell gate66 (
+ .a (net94),
+ .b (net90),
+ .out (net95)
+ );
+ or_cell gate67 (
+ .a (net93),
+ .b (net95),
+ .out (net89)
+ );
+ not_cell gate68 (
+ .in (net92),
+ .out (net94)
+ );
+ and_cell gate69 (
+ .a (net80),
+ .b (net84),
+ .out (net96)
+ );
+ and_cell gate70 (
+ .a (net5),
+ .b (net85),
+ .out (net97)
+ );
+ or_cell gate71 (
+ .a (net96),
+ .b (net97),
+ .out (net92)
+ );
+ dff_cell flipflop12 (
+ .d (net98),
+ .clk (net83),
+ .q (net99),
+ .notq (net100)
+ );
+ and_cell gate72 (
+ .a (net100),
+ .b (net101),
+ .out (net102)
+ );
+ and_cell gate73 (
+ .a (net103),
+ .b (net99),
+ .out (net104)
+ );
+ or_cell gate74 (
+ .a (net102),
+ .b (net104),
+ .out (net98)
+ );
+ not_cell gate75 (
+ .in (net101),
+ .out (net103)
+ );
+ and_cell gate76 (
+ .a (net96),
+ .b (net90),
+ .out (net105)
+ );
+ and_cell gate77 (
+ .a (net91),
+ .b (net97),
+ .out (net106)
+ );
+ or_cell gate78 (
+ .a (net105),
+ .b (net106),
+ .out (net101)
+ );
+ dff_cell flipflop13 (
+ .d (net107),
+ .clk (net83),
+ .q (net108),
+ .notq (net109)
+ );
+ and_cell gate79 (
+ .a (net109),
+ .b (net110),
+ .out (net111)
+ );
+ and_cell gate80 (
+ .a (net112),
+ .b (net108),
+ .out (net113)
+ );
+ or_cell gate81 (
+ .a (net111),
+ .b (net113),
+ .out (net107)
+ );
+ not_cell gate82 (
+ .in (net110),
+ .out (net112)
+ );
+ and_cell gate83 (
+ .a (net105),
+ .b (net99),
+ .out (net114)
+ );
+ and_cell gate84 (
+ .a (net100),
+ .b (net106),
+ .out (net115)
+ );
+ or_cell gate85 (
+ .a (net114),
+ .b (net115),
+ .out (net110)
+ );
+ dff_cell flipflop14 (
+ .d (net116),
+ .clk (net83),
+ .q (net117),
+ .notq (net118)
+ );
+ and_cell gate86 (
+ .a (net118),
+ .b (net119),
+ .out (net120)
+ );
+ and_cell gate87 (
+ .a (net121),
+ .b (net117),
+ .out (net122)
+ );
+ or_cell gate88 (
+ .a (net120),
+ .b (net122),
+ .out (net116)
+ );
+ not_cell gate89 (
+ .in (net119),
+ .out (net121)
+ );
+ and_cell gate90 (
+ .a (net114),
+ .b (net108),
+ .out (net123)
+ );
+ and_cell gate91 (
+ .a (net109),
+ .b (net115),
+ .out (net124)
+ );
+ or_cell gate92 (
+ .a (net123),
+ .b (net124),
+ .out (net119)
+ );
+ dff_cell flipflop15 (
+ .d (net125),
+ .clk (net83),
+ .q (net126),
+ .notq (net127)
+ );
+ and_cell gate93 (
+ .a (net127),
+ .b (net128),
+ .out (net129)
+ );
+ and_cell gate94 (
+ .a (net130),
+ .b (net126),
+ .out (net131)
+ );
+ or_cell gate95 (
+ .a (net129),
+ .b (net131),
+ .out (net125)
+ );
+ not_cell gate96 (
+ .in (net128),
+ .out (net130)
+ );
+ and_cell gate97 (
+ .a (net123),
+ .b (net117),
+ .out (net132)
+ );
+ and_cell gate98 (
+ .a (net118),
+ .b (net124),
+ .out (net133)
+ );
+ or_cell gate99 (
+ .a (net132),
+ .b (net133),
+ .out (net128)
+ );
+ dff_cell flipflop16 (
+ .d (net134),
+ .clk (net83),
+ .q (net135),
+ .notq (net136)
+ );
+ and_cell gate100 (
+ .a (net136),
+ .b (net137),
+ .out (net138)
+ );
+ and_cell gate101 (
+ .a (net139),
+ .b (net135),
+ .out (net140)
+ );
+ or_cell gate102 (
+ .a (net138),
+ .b (net140),
+ .out (net134)
+ );
+ not_cell gate103 (
+ .in (net137),
+ .out (net139)
+ );
+ and_cell gate104 (
+ .a (net132),
+ .b (net126),
+ .out (net141)
+ );
+ and_cell gate105 (
+ .a (net127),
+ .b (net133),
+ .out (net142)
+ );
+ or_cell gate106 (
+ .a (net141),
+ .b (net142),
+ .out (net137)
+ );
+ dff_cell flipflop17 (
+ .d (net143),
+ .clk (net83),
+ .q (net144),
+ .notq (net145)
+ );
+ and_cell gate107 (
+ .a (net145),
+ .b (net146),
+ .out (net147)
+ );
+ and_cell gate108 (
+ .a (net148),
+ .b (net144),
+ .out (net149)
+ );
+ or_cell gate109 (
+ .a (net147),
+ .b (net149),
+ .out (net143)
+ );
+ not_cell gate110 (
+ .in (net146),
+ .out (net148)
+ );
+ and_cell gate111 (
+ .a (net141),
+ .b (net135),
+ .out (net150)
+ );
+ and_cell gate112 (
+ .a (net136),
+ .b (net142),
+ .out (net151)
+ );
+ or_cell gate113 (
+ .a (net150),
+ .b (net151),
+ .out (net146)
+ );
+ and_cell gate115 (
+ .a (net1),
+ .b (net4),
+ .out (net10)
+ );
+ and_cell gate116 (
+ .a (net153),
+ .b (net1),
+ .out (net83)
+ );
+ not_cell gate117 (
+ .in (net4),
+ .out (net153)
+ );
+ not_cell gate118 (
+
+ );
+ not_cell gate130 (
+
+ );
+ not_cell gate131 (
+
+ );
+ buffer_cell gate132 (
+ .in (net154),
+ .out (net155)
+ );
+ buffer_cell gate133 (
+ .in (net156),
+ .out (net157)
+ );
+ buffer_cell gate134 (
+ .in (net158),
+ .out (net159)
+ );
+ buffer_cell gate135 (
+ .in (net160),
+ .out (net161)
+ );
+ not_cell gate136 (
+ .in (net159),
+ .out (net162)
+ );
+ not_cell gate137 (
+ .in (net161),
+ .out (net163)
+ );
+ not_cell gate138 (
+ .in (net157),
+ .out (net164)
+ );
+ not_cell gate139 (
+ .in (net155),
+ .out (net165)
+ );
+ and_cell gate140 (
+ .a (net159),
+ .b (net166),
+ .out (net167)
+ );
+ and_cell gate141 (
+ .a (net165),
+ .b (net157),
+ .out (net166)
+ );
+ or_cell gate142 (
+ .a (net168),
+ .b (net169),
+ .out (net170)
+ );
+ and_cell gate143 (
+ .a (net155),
+ .b (net162),
+ .out (net171)
+ );
+ and_cell gate144 (
+ .a (net163),
+ .b (net172),
+ .out (net173)
+ );
+ and_cell gate145 (
+ .a (net164),
+ .b (net155),
+ .out (net172)
+ );
+ and_cell gate146 (
+ .a (net161),
+ .b (net165),
+ .out (net174)
+ );
+ and_cell gate147 (
+ .a (net157),
+ .b (net161),
+ .out (net175)
+ );
+ or_cell gate148 (
+ .a (net176),
+ .b (net175),
+ .out (net177)
+ );
+ or_cell gate149 (
+ .a (net174),
+ .b (net167),
+ .out (net178)
+ );
+ or_cell gate150 (
+ .a (net173),
+ .b (net171),
+ .out (net169)
+ );
+ or_cell gate151 (
+ .a (net177),
+ .b (net178),
+ .out (net168)
+ );
+ and_cell gate152 (
+ .a (net155),
+ .b (net179),
+ .out (net180)
+ );
+ and_cell gate153 (
+ .a (net163),
+ .b (net159),
+ .out (net179)
+ );
+ and_cell gate154 (
+ .a (net164),
+ .b (net162),
+ .out (net176)
+ );
+ and_cell gate155 (
+ .a (net165),
+ .b (net181),
+ .out (net182)
+ );
+ and_cell gate156 (
+ .a (net163),
+ .b (net162),
+ .out (net181)
+ );
+ and_cell gate157 (
+ .a (net165),
+ .b (net161),
+ .out (net183)
+ );
+ and_cell gate158 (
+ .a (net183),
+ .b (net159),
+ .out (net184)
+ );
+ and_cell gate159 (
+ .a (net165),
+ .b (net164),
+ .out (net185)
+ );
+ or_cell gate160 (
+ .a (net180),
+ .b (net185),
+ .out (net186)
+ );
+ or_cell gate161 (
+ .a (net184),
+ .b (net182),
+ .out (net187)
+ );
+ or_cell gate162 (
+ .a (net186),
+ .b (net187),
+ .out (net188)
+ );
+ or_cell gate163 (
+ .a (net188),
+ .b (net176),
+ .out (net189)
+ );
+ and_cell gate164 (
+ .a (net155),
+ .b (net164),
+ .out (net190)
+ );
+ and_cell gate165 (
+ .a (net165),
+ .b (net157),
+ .out (net191)
+ );
+ and_cell gate166 (
+ .a (net165),
+ .b (net163),
+ .out (net192)
+ );
+ and_cell gate167 (
+ .a (net165),
+ .b (net159),
+ .out (net193)
+ );
+ and_cell gate168 (
+ .a (net159),
+ .b (net163),
+ .out (net194)
+ );
+ or_cell gate169 (
+ .a (net190),
+ .b (net191),
+ .out (net195)
+ );
+ or_cell gate170 (
+ .a (net192),
+ .b (net193),
+ .out (net196)
+ );
+ or_cell gate171 (
+ .a (net195),
+ .b (net196),
+ .out (net197)
+ );
+ or_cell gate172 (
+ .a (net197),
+ .b (net194),
+ .out (net198)
+ );
+ and_cell gate173 (
+ .a (net157),
+ .b (net163),
+ .out (net199)
+ );
+ and_cell gate174 (
+ .a (net165),
+ .b (net161),
+ .out (net200)
+ );
+ and_cell gate175 (
+ .a (net155),
+ .b (net157),
+ .out (net201)
+ );
+ and_cell gate176 (
+ .a (net199),
+ .b (net159),
+ .out (net202)
+ );
+ and_cell gate177 (
+ .a (net200),
+ .b (net162),
+ .out (net203)
+ );
+ and_cell gate178 (
+ .a (net201),
+ .b (net162),
+ .out (net204)
+ );
+ and_cell gate179 (
+ .a (net164),
+ .b (net163),
+ .out (net205)
+ );
+ and_cell gate180 (
+ .a (net164),
+ .b (net161),
+ .out (net206)
+ );
+ and_cell gate181 (
+ .a (net205),
+ .b (net162),
+ .out (net207)
+ );
+ and_cell gate182 (
+ .a (net206),
+ .b (net159),
+ .out (net208)
+ );
+ or_cell gate183 (
+ .a (net204),
+ .b (net203),
+ .out (net209)
+ );
+ or_cell gate184 (
+ .a (net202),
+ .b (net208),
+ .out (net210)
+ );
+ or_cell gate185 (
+ .a (net209),
+ .b (net210),
+ .out (net211)
+ );
+ or_cell gate186 (
+ .a (net211),
+ .b (net207),
+ .out (net212)
+ );
+ and_cell gate187 (
+ .a (net155),
+ .b (net161),
+ .out (net213)
+ );
+ and_cell gate188 (
+ .a (net155),
+ .b (net157),
+ .out (net214)
+ );
+ and_cell gate189 (
+ .a (net161),
+ .b (net162),
+ .out (net215)
+ );
+ or_cell gate190 (
+ .a (net214),
+ .b (net213),
+ .out (net216)
+ );
+ or_cell gate191 (
+ .a (net176),
+ .b (net215),
+ .out (net217)
+ );
+ or_cell gate192 (
+ .a (net216),
+ .b (net217),
+ .out (net218)
+ );
+ and_cell gate193 (
+ .a (net155),
+ .b (net164),
+ .out (net219)
+ );
+ and_cell gate194 (
+ .a (net192),
+ .b (net157),
+ .out (net220)
+ );
+ and_cell gate195 (
+ .a (net157),
+ .b (net162),
+ .out (net221)
+ );
+ or_cell gate196 (
+ .a (net219),
+ .b (net213),
+ .out (net222)
+ );
+ or_cell gate197 (
+ .a (net220),
+ .b (net221),
+ .out (net223)
+ );
+ or_cell gate198 (
+ .a (net222),
+ .b (net223),
+ .out (net224)
+ );
+ or_cell gate199 (
+ .a (net224),
+ .b (net181),
+ .out (net225)
+ );
+ and_cell gate200 (
+ .a (net219),
+ .b (net226),
+ .out (net227)
+ );
+ and_cell gate201 (
+ .a (net155),
+ .b (net159),
+ .out (net228)
+ );
+ or_cell gate202 (
+ .a (net219),
+ .b (net220),
+ .out (net229)
+ );
+ or_cell gate203 (
+ .a (net228),
+ .b (net230),
+ .out (net231)
+ );
+ and_cell gate204 (
+ .a (net164),
+ .b (net161),
+ .out (net230)
+ );
+ or_cell gate205 (
+ .a (net229),
+ .b (net231),
+ .out (net232)
+ );
+ or_cell gate206 (
+ .a (net215),
+ .b (net232),
+ .out (net233)
+ );
+ and_cell gate207 (
+ .a (net161),
+ .b (net159),
+ .out (net226)
+ );
+ mux_cell mux5 (
+ .a (net11),
+ .b (net84),
+ .sel (net235),
+ .out (net236)
+ );
+ or_cell gate208 (
+ .a (net237),
+ .b (net238),
+ .out (net158)
+ );
+ not_cell gate209 (
+ .in (net2),
+ .out (net239)
+ );
+ and_cell gate210 (
+ .a (net2),
+ .b (net240),
+ .out (net241)
+ );
+ mux_cell mux6 (
+ .a (net36),
+ .b (net108),
+ .sel (net235),
+ .out (net242)
+ );
+ mux_cell mux7 (
+ .a (net27),
+ .b (net99),
+ .sel (net235),
+ .out (net243)
+ );
+ mux_cell mux8 (
+ .a (net17),
+ .b (net90),
+ .sel (net235),
+ .out (net240)
+ );
+ mux_cell mux9 (
+ .a (net45),
+ .b (net117),
+ .sel (net235),
+ .out (net244)
+ );
+ mux_cell mux10 (
+ .a (net72),
+ .b (net144),
+ .sel (net235),
+ .out (net245)
+ );
+ mux_cell mux11 (
+ .a (net63),
+ .b (net135),
+ .sel (net235),
+ .out (net246)
+ );
+ mux_cell mux12 (
+ .a (net54),
+ .b (net126),
+ .sel (net235),
+ .out (net247)
+ );
+ and_cell gate211 (
+ .a (net2),
+ .b (net236),
+ .out (net237)
+ );
+ and_cell gate212 (
+ .a (net2),
+ .b (net243),
+ .out (net248)
+ );
+ and_cell gate213 (
+ .a (net2),
+ .b (net242),
+ .out (net249)
+ );
+ and_cell gate214 (
+ .a (net250),
+ .b (net247),
+ .out (net251)
+ );
+ and_cell gate215 (
+ .a (net239),
+ .b (net244),
+ .out (net238)
+ );
+ and_cell gate216 (
+ .a (net252),
+ .b (net246),
+ .out (net253)
+ );
+ and_cell gate217 (
+ .a (net254),
+ .b (net245),
+ .out (net255)
+ );
+ not_cell gate218 (
+ .in (net2),
+ .out (net250)
+ );
+ not_cell gate219 (
+ .in (net2),
+ .out (net252)
+ );
+ not_cell gate220 (
+ .in (net2),
+ .out (net254)
+ );
+ or_cell gate221 (
+ .a (net249),
+ .b (net255),
+ .out (net154)
+ );
+ or_cell gate222 (
+ .a (net248),
+ .b (net253),
+ .out (net156)
+ );
+ or_cell gate223 (
+ .a (net241),
+ .b (net251),
+ .out (net160)
+ );
+ not_cell not1 (
+ .in (net3),
+ .out (net235)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_349546262775726676.v b/verilog/rtl/user_module_349546262775726676.v
new file mode 100644
index 0000000..a8397d4
--- /dev/null
+++ b/verilog/rtl/user_module_349546262775726676.v
@@ -0,0 +1,310 @@
+/* Automatically generated from https://wokwi.com/projects/349546262775726676 */
+
+`default_nettype none
+
+module user_module_349546262775726676(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[0];
+ wire net2 = io_in[1];
+ wire net3 = io_in[2];
+ wire net4 = io_in[3];
+ wire net5 = io_in[4];
+ wire net6 = io_in[5];
+ wire net7;
+ wire net8;
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15 = 1'b0;
+ wire net16 = 1'b1;
+ wire net17 = 1'b1;
+ wire net18;
+ wire net19;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
+ wire net49;
+ wire net50;
+ wire net51;
+ wire net52;
+ wire net53;
+
+ assign io_out[0] = net7;
+ assign io_out[1] = net8;
+ assign io_out[2] = net9;
+ assign io_out[3] = net10;
+ assign io_out[4] = net11;
+ assign io_out[5] = net12;
+ assign io_out[6] = net13;
+ assign io_out[7] = net14;
+
+ and_cell gate1 (
+
+ );
+ or_cell gate2 (
+
+ );
+ xor_cell gate3 (
+
+ );
+ nand_cell gate4 (
+
+ );
+ not_cell gate5 (
+
+ );
+ buffer_cell gate6 (
+
+ );
+ mux_cell mux1 (
+
+ );
+ dff_cell flipflop1 (
+
+ );
+ buffer_cell gate7 (
+ .in (net4),
+ .out (net18)
+ );
+ buffer_cell gate8 (
+ .in (net3),
+ .out (net19)
+ );
+ buffer_cell gate9 (
+ .in (net2),
+ .out (net20)
+ );
+ buffer_cell gate10 (
+ .in (net1),
+ .out (net21)
+ );
+ not_cell gate11 (
+ .in (net4)
+ );
+ not_cell gate12 (
+ .in (net3),
+ .out (net22)
+ );
+ not_cell gate13 (
+ .in (net2),
+ .out (net23)
+ );
+ not_cell gate14 (
+ .in (net1),
+ .out (net24)
+ );
+ and_cell gate15 (
+ .a (net19),
+ .b (net21),
+ .out (net25)
+ );
+ and_cell gate16 (
+ .a (net22),
+ .b (net24),
+ .out (net26)
+ );
+ and_cell gate17 (
+ .a (net20),
+ .b (net21),
+ .out (net27)
+ );
+ and_cell gate18 (
+ .a (net23),
+ .b (net24),
+ .out (net28)
+ );
+ and_cell gate19 (
+ .a (net20),
+ .b (net24),
+ .out (net29)
+ );
+ and_cell gate20 (
+ .a (net22),
+ .b (net20),
+ .out (net30)
+ );
+ and_cell gate21 (
+ .a (net21),
+ .b (net31),
+ .out (net32)
+ );
+ and_cell gate22 (
+ .a (net19),
+ .b (net23),
+ .out (net31)
+ );
+ and_cell gate23 (
+ .a (net19),
+ .b (net24),
+ .out (net33)
+ );
+ or_cell gate24 (
+ .a (net25),
+ .b (net26),
+ .out (net34)
+ );
+ or_cell gate25 (
+ .a (net18),
+ .b (net20),
+ .out (net35)
+ );
+ or_cell gate26 (
+ .a (net34),
+ .b (net35),
+ .out (net36)
+ );
+ or_cell gate27 (
+ .a (net27),
+ .b (net28),
+ .out (net37)
+ );
+ or_cell gate28 (
+ .a (net37),
+ .b (net22),
+ .out (net38)
+ );
+ or_cell gate29 (
+ .a (net19),
+ .b (net23),
+ .out (net39)
+ );
+ or_cell gate30 (
+ .a (net39),
+ .b (net21),
+ .out (net40)
+ );
+ or_cell gate31 (
+ .a (net18),
+ .b (net26),
+ .out (net41)
+ );
+ or_cell gate32 (
+ .a (net29),
+ .b (net30),
+ .out (net42)
+ );
+ or_cell gate33 (
+ .a (net41),
+ .b (net42),
+ .out (net43)
+ );
+ or_cell gate34 (
+ .a (net43),
+ .b (net32),
+ .out (net44)
+ );
+ or_cell gate35 (
+ .a (net26),
+ .b (net29),
+ .out (net45)
+ );
+ or_cell gate36 (
+ .a (net31),
+ .b (net33),
+ .out (net46)
+ );
+ or_cell gate37 (
+ .a (net28),
+ .b (net18),
+ .out (net47)
+ );
+ or_cell gate38 (
+ .a (net46),
+ .b (net47),
+ .out (net48)
+ );
+ or_cell gate39 (
+ .a (net29),
+ .b (net30),
+ .out (net49)
+ );
+ or_cell gate40 (
+ .a (net31),
+ .b (net18),
+ .out (net50)
+ );
+ or_cell gate41 (
+ .a (net49),
+ .b (net50),
+ .out (net51)
+ );
+ buffer_cell gate42 (
+ .in (net5),
+ .out (net52)
+ );
+ xor_cell gate45 (
+ .a (net52),
+ .b (net53),
+ .out (net14)
+ );
+ xor_cell gate44 (
+ .a (net36),
+ .b (net53),
+ .out (net7)
+ );
+ buffer_cell gate43 (
+ .in (net6),
+ .out (net53)
+ );
+ xor_cell gate46 (
+ .a (net38),
+ .b (net53),
+ .out (net8)
+ );
+ xor_cell gate47 (
+ .a (net40),
+ .b (net53),
+ .out (net9)
+ );
+ xor_cell gate48 (
+ .a (net44),
+ .b (net53),
+ .out (net10)
+ );
+ xor_cell gate49 (
+ .a (net45),
+ .b (net53),
+ .out (net11)
+ );
+ xor_cell gate50 (
+ .a (net48),
+ .b (net53),
+ .out (net12)
+ );
+ xor_cell gate51 (
+ .a (net51),
+ .b (net53),
+ .out (net13)
+ );
+endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 0f19ff9..43f8b90 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -1473,7 +1473,7 @@
.module_data_out (sw_061_module_data_out)
);
- user_module_348953272198890067 user_module_348953272198890067_061 (
+ user_module_349405063877231188 user_module_349405063877231188_061 (
.io_in (sw_061_module_data_in),
.io_out (sw_061_module_data_out)
);
@@ -1918,7 +1918,7 @@
.io_out (sw_081_module_data_out)
);
- // [082] https://github.com/TinyTapeout/tt02-test-invert
+ // [082] https://github.com/youngpines/tt02-youngpines-submission
wire sw_082_clk_out, sw_082_data_out, sw_082_scan_out, sw_082_latch_out;
wire [7:0] sw_082_module_data_in;
wire [7:0] sw_082_module_data_out;
@@ -1935,12 +1935,12 @@
.module_data_out (sw_082_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_082 (
+ user_module_341571228858843732 user_module_341571228858843732_082 (
.io_in (sw_082_module_data_in),
.io_out (sw_082_module_data_out)
);
- // [083] https://github.com/TinyTapeout/tt02-test-invert
+ // [083] https://github.com/timvgso/tinatapeworm
wire sw_083_clk_out, sw_083_data_out, sw_083_scan_out, sw_083_latch_out;
wire [7:0] sw_083_module_data_in;
wire [7:0] sw_083_module_data_out;
@@ -1957,12 +1957,12 @@
.module_data_out (sw_083_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_083 (
+ user_module_348381622440034899 user_module_348381622440034899_083 (
.io_in (sw_083_module_data_in),
.io_out (sw_083_module_data_out)
);
- // [084] https://github.com/TinyTapeout/tt02-test-invert
+ // [084] https://github.com/OneRNG/tt-cpu8
wire sw_084_clk_out, sw_084_data_out, sw_084_scan_out, sw_084_latch_out;
wire [7:0] sw_084_module_data_in;
wire [7:0] sw_084_module_data_out;
@@ -1979,12 +1979,12 @@
.module_data_out (sw_084_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_084 (
+ moonbase_cpu_8bit moonbase_cpu_8bit_084 (
.io_in (sw_084_module_data_in),
.io_out (sw_084_module_data_out)
);
- // [085] https://github.com/TinyTapeout/tt02-test-invert
+ // [085] https://github.com/tcptomato/tt02-submission-template
wire sw_085_clk_out, sw_085_data_out, sw_085_scan_out, sw_085_latch_out;
wire [7:0] sw_085_module_data_in;
wire [7:0] sw_085_module_data_out;
@@ -2001,12 +2001,12 @@
.module_data_out (sw_085_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_085 (
+ user_module_341178154799333971 user_module_341178154799333971_085 (
.io_in (sw_085_module_data_in),
.io_out (sw_085_module_data_out)
);
- // [086] https://github.com/TinyTapeout/tt02-test-invert
+ // [086] https://github.com/jglim/tt02-bcd-7seg
wire sw_086_clk_out, sw_086_data_out, sw_086_scan_out, sw_086_latch_out;
wire [7:0] sw_086_module_data_in;
wire [7:0] sw_086_module_data_out;
@@ -2023,12 +2023,12 @@
.module_data_out (sw_086_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_086 (
+ user_module_349546262775726676 user_module_349546262775726676_086 (
.io_in (sw_086_module_data_in),
.io_out (sw_086_module_data_out)
);
- // [087] https://github.com/TinyTapeout/tt02-test-invert
+ // [087] https://github.com/ARamsey118/tiny_tapeout_freq_counter
wire sw_087_clk_out, sw_087_data_out, sw_087_scan_out, sw_087_latch_out;
wire [7:0] sw_087_module_data_in;
wire [7:0] sw_087_module_data_out;
@@ -2045,12 +2045,12 @@
.module_data_out (sw_087_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_087 (
+ aramsey118_freq_counter aramsey118_freq_counter_087 (
.io_in (sw_087_module_data_in),
.io_out (sw_087_module_data_out)
);
- // [088] https://github.com/TinyTapeout/tt02-test-invert
+ // [088] https://github.com/splinedrive/thunderbird_taillight_1965
wire sw_088_clk_out, sw_088_data_out, sw_088_scan_out, sw_088_latch_out;
wire [7:0] sw_088_module_data_in;
wire [7:0] sw_088_module_data_out;
@@ -2067,12 +2067,12 @@
.module_data_out (sw_088_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_088 (
+ thunderbird_taillight_ctrl thunderbird_taillight_ctrl_088 (
.io_in (sw_088_module_data_in),
.io_out (sw_088_module_data_out)
);
- // [089] https://github.com/TinyTapeout/tt02-test-invert
+ // [089] https://github.com/gatecat/tt02-fpga-respin
wire sw_089_clk_out, sw_089_data_out, sw_089_scan_out, sw_089_latch_out;
wire [7:0] sw_089_module_data_in;
wire [7:0] sw_089_module_data_out;
@@ -2089,12 +2089,12 @@
.module_data_out (sw_089_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_089 (
+ gatecat_fpga_top gatecat_fpga_top_089 (
.io_in (sw_089_module_data_in),
.io_out (sw_089_module_data_out)
);
- // [090] https://github.com/TinyTapeout/tt02-test-invert
+ // [090] https://github.com/mmolteni-secpat/tinytapeout02_chi2shares
wire sw_090_clk_out, sw_090_data_out, sw_090_scan_out, sw_090_latch_out;
wire [7:0] sw_090_module_data_in;
wire [7:0] sw_090_module_data_out;
@@ -2111,12 +2111,12 @@
.module_data_out (sw_090_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_090 (
+ user_module_341589685194195540 user_module_341589685194195540_090 (
.io_in (sw_090_module_data_in),
.io_out (sw_090_module_data_out)
);
- // [091] https://github.com/TinyTapeout/tt02-test-invert
+ // [091] https://github.com/mmolteni-secpat/tinytapeout02_chi3shares
wire sw_091_clk_out, sw_091_data_out, sw_091_scan_out, sw_091_latch_out;
wire [7:0] sw_091_module_data_in;
wire [7:0] sw_091_module_data_out;
@@ -2133,12 +2133,12 @@
.module_data_out (sw_091_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_091 (
+ user_module_341608574336631379 user_module_341608574336631379_091 (
.io_in (sw_091_module_data_in),
.io_out (sw_091_module_data_out)
);
- // [092] https://github.com/TinyTapeout/tt02-test-invert
+ // [092] https://github.com/Wren6991/tt02-whisk-serial-processor
wire sw_092_clk_out, sw_092_data_out, sw_092_scan_out, sw_092_latch_out;
wire [7:0] sw_092_module_data_in;
wire [7:0] sw_092_module_data_out;
@@ -2155,12 +2155,12 @@
.module_data_out (sw_092_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_092 (
+ wren6991_whisk_tt2_io_wrapper wren6991_whisk_tt2_io_wrapper_092 (
.io_in (sw_092_module_data_in),
.io_out (sw_092_module_data_out)
);
- // [093] https://github.com/TinyTapeout/tt02-test-invert
+ // [093] https://github.com/aiunderstand/tt02-4bit-tristate-loadable-counter
wire sw_093_clk_out, sw_093_data_out, sw_093_scan_out, sw_093_latch_out;
wire [7:0] sw_093_module_data_in;
wire [7:0] sw_093_module_data_out;
@@ -2177,12 +2177,12 @@
.module_data_out (sw_093_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_093 (
+ user_module_341423712597181012 user_module_341423712597181012_093 (
.io_in (sw_093_module_data_in),
.io_out (sw_093_module_data_out)
);
- // [094] https://github.com/TinyTapeout/tt02-test-invert
+ // [094] https://github.com/aiunderstand/tt02-async-binary-ternary-convert-compare
wire sw_094_clk_out, sw_094_data_out, sw_094_scan_out, sw_094_latch_out;
wire [7:0] sw_094_module_data_in;
wire [7:0] sw_094_module_data_out;
@@ -2199,12 +2199,12 @@
.module_data_out (sw_094_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_094 (
+ user_module_341277789473735250 user_module_341277789473735250_094 (
.io_in (sw_094_module_data_in),
.io_out (sw_094_module_data_out)
);
- // [095] https://github.com/TinyTapeout/tt02-test-invert
+ // [095] https://github.com/RobertRiachi/tt02-dot-product
wire sw_095_clk_out, sw_095_data_out, sw_095_scan_out, sw_095_latch_out;
wire [7:0] sw_095_module_data_in;
wire [7:0] sw_095_module_data_out;
@@ -2221,7 +2221,7 @@
.module_data_out (sw_095_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_095 (
+ user_module_348787952842703444 user_module_348787952842703444_095 (
.io_in (sw_095_module_data_in),
.io_out (sw_095_module_data_out)
);
