Merge branch 'zigzag-scan-chain' into mpw7
diff --git a/INFO.md b/INFO.md
index 4bee4e5..9abbc17 100644
--- a/INFO.md
+++ b/INFO.md
@@ -76,6 +76,8 @@
There are some testbenches that you can use to check the scan chain and controller is working.
The default of 498 projects takes a very long time to simulate, so I advise overriding the configuration first:
+ # fetch the test projects
+ ./configure.py --test --update-projects
# rebuild config with only 20 projects
./configure.py --test --update-caravel --limit 20
@@ -85,8 +87,17 @@
# you will also need to set your PDK_ROOT environment variable
make test_scan_controller
-The Gate Level version (requires scan_controller and user_project_wrapper to be re-hardened to get the correct gate level netlists. These files are avaialable in the gl_test branch).
+The Gate Level simulation requires scan_controller and user_project_wrapper to be re-hardened to get the correct gate level netlists:
+* Edit openlane/scan_controller/config.tcl and change NUM_DESIGNS=498 to NUM_DESIGNS=20.
+* Then from the top level directory:
+
+ make scan_controller
+ make user_project_wrapper
+
+* Then run the GL test
+
+ cd verilog/dv/scan_controller
make test_scan_controller_gl
### Top level test: internal control
diff --git a/verilog/dv/scan_controller/test_scan_controller.py b/verilog/dv/scan_controller/test_scan_controller.py
index b9d96e1..1a1be2f 100644
--- a/verilog/dv/scan_controller/test_scan_controller.py
+++ b/verilog/dv/scan_controller/test_scan_controller.py
@@ -56,7 +56,7 @@
dut.inputs.value = 0
# sync to display, GL and RTL have different times to start
- print("sync to display")
+ print("sync to 7seg at pos 1")
count = 10
while count > 0:
await FallingEdge(dut.slow_clk)
@@ -70,7 +70,7 @@
assert decode_seg(dut.seven_seg.value) == i
await FallingEdge(dut.slow_clk)
- print("straight test")
+ print("straight test at pos 0")
dut.set_clk_div.value = 0 # no clock div
dut.active_select.value = 0 # straight
await FallingEdge(dut.ready)
@@ -81,7 +81,7 @@
if i > 0:
assert i == int(dut.outputs) + 1
- print("invert test")
+ print("invert test at pos 2")
dut.active_select.value = 2 # invert
dut.inputs.value = 0
await FallingEdge(dut.ready)
@@ -93,9 +93,9 @@
if i > 0:
assert 256 - i == int(dut.outputs)
- for design in range(10): # next 10 designs are all straight
+ for design in range(3,20): # next designs are all straight
print("straight test at pos {}".format(design))
- dut.active_select.value = 3 + design
+ dut.active_select.value = design
await FallingEdge(dut.ready)
for i in range(11):
dut.inputs.value = i
diff --git a/verilog/dv/scan_controller_ext/scan_controller.c b/verilog/dv/scan_controller_ext/scan_controller.c
index 6edea7e..797bcfd 100644
--- a/verilog/dv/scan_controller_ext/scan_controller.c
+++ b/verilog/dv/scan_controller_ext/scan_controller.c
@@ -51,9 +51,12 @@
outputs (io_out[36:29]),
ext_scan_clk = inputs[0];
ext_scan_data_in = inputs[1];
- ext_scan_data_out = outputs[0]
+ ext_scan_clk_in = outputs[0]
+ ext_scan_data_in = outputs[1]
ext_scan_select = inputs[2];
ext_scan_latch_en = inputs[3];
+
+ assign outputs = driver_sel[1] ? aio_output_reg : {6'b0, ext_scan_data_in, ext_scan_clk_in};
*/
reg_mprj_io_21 = GPIO_MODE_USER_STD_INPUT_NOPULL; // clk
@@ -61,7 +64,8 @@
reg_mprj_io_23 = GPIO_MODE_USER_STD_INPUT_NOPULL; // scan
reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_NOPULL; // latch
- reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT; // data out
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT; // clk out
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT; // data out
// outputs for testbench control
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; // fw ready
diff --git a/verilog/dv/scan_controller_ext/scan_controller.hex b/verilog/dv/scan_controller_ext/scan_controller.hex
index 4dd92e8..d81258e 100755
--- a/verilog/dv/scan_controller_ext/scan_controller.hex
+++ b/verilog/dv/scan_controller_ext/scan_controller.hex
@@ -12,7 +12,7 @@
03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30
17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6
73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00
-13 06 46 2D 63 0C B5 00 83 26 06 00 23 20 D5 00
+13 06 C6 2E 63 0C B5 00 83 26 06 00 23 20 D5 00
13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00
93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00
6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30
@@ -51,9 +51,11 @@
13 07 20 40 23 A0 E7 00 B7 07 00 26 93 87 47 08
13 07 20 40 23 A0 E7 00 B7 07 00 26 93 87 87 09
37 27 00 00 13 07 87 80 23 A0 E7 00 B7 07 00 26
-93 87 47 05 37 27 00 00 13 07 97 80 23 A0 E7 00
-B7 07 00 26 13 07 10 00 23 A0 E7 00 13 00 00 00
-B7 07 00 26 03 A7 07 00 93 07 10 00 E3 0A F7 FE
-B7 07 00 26 93 87 C7 00 83 A6 07 00 B7 07 00 26
-93 87 C7 00 37 17 00 00 33 E7 E6 00 23 A0 E7 00
-13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00
+93 87 C7 09 37 27 00 00 13 07 87 80 23 A0 E7 00
+B7 07 00 26 93 87 47 05 37 27 00 00 13 07 97 80
+23 A0 E7 00 B7 07 00 26 13 07 10 00 23 A0 E7 00
+13 00 00 00 B7 07 00 26 03 A7 07 00 93 07 10 00
+E3 0A F7 FE B7 07 00 26 93 87 C7 00 83 A6 07 00
+B7 07 00 26 93 87 C7 00 37 17 00 00 33 E7 E6 00
+23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01
+67 80 00 00
diff --git a/verilog/dv/scan_controller_ext/scan_controller_ext.gtkw b/verilog/dv/scan_controller_ext/scan_controller_ext.gtkw
index c4a3411..64a7b90 100644
--- a/verilog/dv/scan_controller_ext/scan_controller_ext.gtkw
+++ b/verilog/dv/scan_controller_ext/scan_controller_ext.gtkw
@@ -1,22 +1,22 @@
[*]
-[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
-[*] Sun Aug 28 03:59:31 2022
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Fri Sep 2 12:46:11 2022
[*]
[dumpfile] "/home/matt/work/asic-workshop/shuttle7/tinytapeout-mpw7/verilog/dv/scan_controller_ext/scan_controller_tb.vcd"
-[dumpfile_mtime] "Sun Aug 28 03:59:25 2022"
-[dumpfile_size] 357948
+[dumpfile_mtime] "Fri Sep 2 12:44:13 2022"
+[dumpfile_size] 381427
[savefile] "/home/matt/work/asic-workshop/shuttle7/tinytapeout-mpw7/verilog/dv/scan_controller_ext/scan_controller_ext.gtkw"
-[timestart] 365159000
-[size] 1848 1016
+[timestart] 384490000
+[size] 2235 1105
[pos] -1 -1
-*-18.000000 366175000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-21.299999 396812500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] scan_controller_tb.
[treeopen] scan_controller_tb.uut.
[treeopen] scan_controller_tb.uut.mprj.
[sst_width] 423
-[signals_width] 261
+[signals_width] 475
[sst_expanded] 1
-[sst_vpaned_height] 254
+[sst_vpaned_height] 280
@28
scan_controller_tb.clk
scan_controller_tb.driver_sel[1:0]
@@ -25,22 +25,23 @@
@800200
-scan chain
@28
-scan_controller_tb.uut.mprj.scan_controller.scan_clk
+scan_controller_tb.uut.mprj.scan_controller.scan_clk_in
+scan_controller_tb.uut.mprj.scan_controller.scan_clk_out
scan_controller_tb.uut.mprj.scan_controller.scan_data_in
scan_controller_tb.uut.mprj.scan_controller.scan_data_out
scan_controller_tb.uut.mprj.scan_controller.scan_latch_en
-scan_controller_tb.uut.mprj.scan_controller.scan_select
@1000200
-scan chain
@800200
-ext scan chain
-@29
+@1000200
+-ext scan chain
+@28
scan_controller_tb.ext_clk
+scan_controller_tb.ext_clk_out
scan_controller_tb.ext_data_in
scan_controller_tb.ext_data_out
scan_controller_tb.ext_latch
scan_controller_tb.ext_scan
-@1000200
--ext scan chain
[pattern_trace] 1
[pattern_trace] 0
diff --git a/verilog/dv/scan_controller_ext/scan_controller_tb.v b/verilog/dv/scan_controller_ext/scan_controller_tb.v
index 9b02c87..13f5270 100644
--- a/verilog/dv/scan_controller_ext/scan_controller_tb.v
+++ b/verilog/dv/scan_controller_ext/scan_controller_tb.v
@@ -37,7 +37,8 @@
///// convenience signals that match what the cocotb test modules are looking for
// change to suit your project. Here's how we can make some nicer named signals for inputs & outputs
wire fw_ready = mprj_io[12];
- wire ext_data_out = mprj_io[29];
+ wire ext_clk_out = mprj_io[29];
+ wire ext_data_out = mprj_io[30];
wire [1:0] driver_sel;
wire ext_clk, ext_latch, ext_scan, ext_data_in;
diff --git a/verilog/dv/scan_controller_ext/test_scan_controller.py b/verilog/dv/scan_controller_ext/test_scan_controller.py
index 40af416..ef469be 100644
--- a/verilog/dv/scan_controller_ext/test_scan_controller.py
+++ b/verilog/dv/scan_controller_ext/test_scan_controller.py
@@ -58,14 +58,13 @@
dut.ext_scan.value = 0
# drive the data out
- for i in range(8):
+ for i in range(8*20):
dut.ext_clk.value = 1
await ClockCycles(dut.clk, 1)
dut.ext_clk.value = 0
await ClockCycles(dut.clk, 1)
- print(dut.ext_data_out.value)
- if i < 4:
+ if i in [152, 153, 154, 155]:
assert(dut.ext_data_out.value == 1)
- else:
+ elif i in [156, 157, 158, 159]:
assert(dut.ext_data_out.value == 0)
diff --git a/verilog/dv/scan_controller_la/scan_controller.c b/verilog/dv/scan_controller_la/scan_controller.c
index 1547b92..633db68 100644
--- a/verilog/dv/scan_controller_la/scan_controller.c
+++ b/verilog/dv/scan_controller_la/scan_controller.c
@@ -32,6 +32,7 @@
#define FW_READY 12
#define FW_DONE 13
#define DATA_RX 14
+#define TB_CLK 15
void main()
{
@@ -59,11 +60,14 @@
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; // fw ready
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT; // fw done
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; // data rx
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; // tb clk
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
+ CLR(reg_mprj_datal, DATA_RX);
+
reg_la0_iena = 0x0; // input enable on
reg_la0_oenb = 0xFFFFFFFF; // enable all of bank0 logic analyser outputs (ignore the name, 1 is on, 0 off)
@@ -87,15 +91,22 @@
// clock the data out of the modules into the chain
SET(reg_la0_data, SCAN);
SET(reg_la0_data, CLK);
- CLR(reg_la0_data, CLK);
CLR(reg_la0_data, SCAN);
+
// wait for some data to arrive
- for(i = 0; i < 8; i ++)
+ for(i = 0; i < 8*20; i ++)
{
SET(reg_la0_data, CLK);
CLR(reg_la0_data, CLK);
- if(GET(reg_la0_data_in, DATA_IN))
- reg_mprj_datal |= 1 << DATA_RX;
+
+ if(GET(reg_la0_data_in, DATA_IN)) // returns 1 even if we see x in the trace
+ SET(reg_mprj_datal, DATA_RX);
+ else
+ CLR(reg_mprj_datal, DATA_RX);
+
+ // sync to tb
+ SET(reg_mprj_datal, TB_CLK);
+ CLR(reg_mprj_datal, TB_CLK);
}
reg_mprj_datal |= 1 << FW_DONE;
diff --git a/verilog/dv/scan_controller_la/scan_controller.hex b/verilog/dv/scan_controller_la/scan_controller.hex
index eada8bf..050e302 100755
--- a/verilog/dv/scan_controller_la/scan_controller.hex
+++ b/verilog/dv/scan_controller_la/scan_controller.hex
@@ -12,7 +12,7 @@
03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30
17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6
73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00
-13 06 46 4D 63 0C B5 00 83 26 06 00 23 20 D5 00
+13 06 C6 55 63 0C B5 00 83 26 06 00 23 20 D5 00
13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00
93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00
6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30
@@ -49,43 +49,52 @@
37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26
93 87 87 05 37 27 00 00 13 07 97 80 23 A0 E7 00
B7 07 00 26 93 87 C7 05 37 27 00 00 13 07 97 80
-23 A0 E7 00 B7 07 00 26 13 07 10 00 23 A0 E7 00
-13 00 00 00 B7 07 00 26 03 A7 07 00 93 07 10 00
-E3 0A F7 FE B7 37 00 F0 93 87 C7 00 23 A0 07 00
-B7 37 00 F0 93 87 C7 01 13 07 F0 FF 23 A0 E7 00
-B7 07 00 26 93 87 C7 00 83 A6 07 00 B7 07 00 26
-93 87 C7 00 37 17 00 00 33 E7 E6 00 23 A0 E7 00
-B7 37 00 F0 93 87 C7 03 03 A7 07 00 B7 37 00 F0
-93 87 C7 03 13 67 27 00 23 A0 E7 00 B7 37 00 F0
-93 87 C7 03 03 A7 07 00 B7 37 00 F0 93 87 C7 03
-13 77 B7 FF 23 A0 E7 00 23 26 04 FE 6F 00 00 07
-B7 37 00 F0 93 87 C7 03 03 A7 07 00 B7 37 00 F0
-93 87 C7 03 13 67 17 00 23 A0 E7 00 B7 37 00 F0
-93 87 C7 03 03 A7 07 00 B7 37 00 F0 93 87 C7 03
-13 77 E7 FF 23 A0 E7 00 03 27 C4 FE 93 07 30 00
-63 10 F7 02 B7 37 00 F0 93 87 C7 03 03 A7 07 00
-B7 37 00 F0 93 87 C7 03 13 77 D7 FF 23 A0 E7 00
-83 27 C4 FE 93 87 17 00 23 26 F4 FE 03 27 C4 FE
-93 07 70 00 E3 D6 E7 F8 B7 37 00 F0 93 87 C7 03
-03 A7 07 00 B7 37 00 F0 93 87 C7 03 13 67 87 00
-23 A0 E7 00 B7 37 00 F0 93 87 C7 03 03 A7 07 00
-B7 37 00 F0 93 87 C7 03 13 77 77 FF 23 A0 E7 00
-B7 37 00 F0 93 87 C7 03 03 A7 07 00 B7 37 00 F0
-93 87 C7 03 13 67 47 00 23 A0 E7 00 B7 37 00 F0
-93 87 C7 03 03 A7 07 00 B7 37 00 F0 93 87 C7 03
-13 67 17 00 23 A0 E7 00 B7 37 00 F0 93 87 C7 03
-03 A7 07 00 B7 37 00 F0 93 87 C7 03 13 77 E7 FF
+23 A0 E7 00 B7 07 00 26 93 87 07 06 37 27 00 00
+13 07 97 80 23 A0 E7 00 B7 07 00 26 13 07 10 00
+23 A0 E7 00 13 00 00 00 B7 07 00 26 03 A7 07 00
+93 07 10 00 E3 0A F7 FE B7 07 00 26 93 87 C7 00
+83 A6 07 00 B7 07 00 26 93 87 C7 00 37 C7 FF FF
+13 07 F7 FF 33 F7 E6 00 23 A0 E7 00 B7 37 00 F0
+93 87 C7 00 23 A0 07 00 B7 37 00 F0 93 87 C7 01
+13 07 F0 FF 23 A0 E7 00 B7 07 00 26 93 87 C7 00
+83 A6 07 00 B7 07 00 26 93 87 C7 00 37 17 00 00
+33 E7 E6 00 23 A0 E7 00 B7 37 00 F0 93 87 C7 03
+03 A7 07 00 B7 37 00 F0 93 87 C7 03 13 67 27 00
23 A0 E7 00 B7 37 00 F0 93 87 C7 03 03 A7 07 00
B7 37 00 F0 93 87 C7 03 13 77 B7 FF 23 A0 E7 00
-23 26 04 FE 6F 00 C0 07 B7 37 00 F0 93 87 C7 03
+23 26 04 FE 6F 00 00 07 B7 37 00 F0 93 87 C7 03
03 A7 07 00 B7 37 00 F0 93 87 C7 03 13 67 17 00
23 A0 E7 00 B7 37 00 F0 93 87 C7 03 03 A7 07 00
B7 37 00 F0 93 87 C7 03 13 77 E7 FF 23 A0 E7 00
-B7 37 00 F0 93 87 C7 02 83 A7 07 00 93 F7 17 00
-63 82 07 02 B7 07 00 26 93 87 C7 00 83 A6 07 00
-B7 07 00 26 93 87 C7 00 37 47 00 00 33 E7 E6 00
-23 A0 E7 00 83 27 C4 FE 93 87 17 00 23 26 F4 FE
-03 27 C4 FE 93 07 70 00 E3 D0 E7 F8 B7 07 00 26
-93 87 C7 00 83 A6 07 00 B7 07 00 26 93 87 C7 00
-37 27 00 00 33 E7 E6 00 23 A0 E7 00 13 00 00 00
-03 24 C1 01 13 01 01 02 67 80 00 00
+03 27 C4 FE 93 07 30 00 63 10 F7 02 B7 37 00 F0
+93 87 C7 03 03 A7 07 00 B7 37 00 F0 93 87 C7 03
+13 77 D7 FF 23 A0 E7 00 83 27 C4 FE 93 87 17 00
+23 26 F4 FE 03 27 C4 FE 93 07 70 00 E3 D6 E7 F8
+B7 37 00 F0 93 87 C7 03 03 A7 07 00 B7 37 00 F0
+93 87 C7 03 13 67 87 00 23 A0 E7 00 B7 37 00 F0
+93 87 C7 03 03 A7 07 00 B7 37 00 F0 93 87 C7 03
+13 77 77 FF 23 A0 E7 00 B7 37 00 F0 93 87 C7 03
+03 A7 07 00 B7 37 00 F0 93 87 C7 03 13 67 47 00
+23 A0 E7 00 B7 37 00 F0 93 87 C7 03 03 A7 07 00
+B7 37 00 F0 93 87 C7 03 13 67 17 00 23 A0 E7 00
+B7 37 00 F0 93 87 C7 03 03 A7 07 00 B7 37 00 F0
+93 87 C7 03 13 77 B7 FF 23 A0 E7 00 23 26 04 FE
+6F 00 80 0E B7 37 00 F0 93 87 C7 03 03 A7 07 00
+B7 37 00 F0 93 87 C7 03 13 67 17 00 23 A0 E7 00
+B7 37 00 F0 93 87 C7 03 03 A7 07 00 B7 37 00 F0
+93 87 C7 03 13 77 E7 FF 23 A0 E7 00 B7 37 00 F0
+93 87 C7 02 83 A7 07 00 93 F7 17 00 63 84 07 02
+B7 07 00 26 93 87 C7 00 83 A6 07 00 B7 07 00 26
+93 87 C7 00 37 47 00 00 33 E7 E6 00 23 A0 E7 00
+6F 00 80 02 B7 07 00 26 93 87 C7 00 83 A6 07 00
+B7 07 00 26 93 87 C7 00 37 C7 FF FF 13 07 F7 FF
+33 F7 E6 00 23 A0 E7 00 B7 07 00 26 93 87 C7 00
+83 A6 07 00 B7 07 00 26 93 87 C7 00 37 87 00 00
+33 E7 E6 00 23 A0 E7 00 B7 07 00 26 93 87 C7 00
+83 A6 07 00 B7 07 00 26 93 87 C7 00 37 87 FF FF
+13 07 F7 FF 33 F7 E6 00 23 A0 E7 00 83 27 C4 FE
+93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 F0 09
+E3 DA E7 F0 B7 07 00 26 93 87 C7 00 83 A6 07 00
+B7 07 00 26 93 87 C7 00 37 27 00 00 33 E7 E6 00
+23 A0 E7 00 13 00 00 00 03 24 C1 01 13 01 01 02
+67 80 00 00
diff --git a/verilog/dv/scan_controller_la/scan_controller_la.gtkw b/verilog/dv/scan_controller_la/scan_controller_la.gtkw
index cf6ba1a..f22c0bc 100644
--- a/verilog/dv/scan_controller_la/scan_controller_la.gtkw
+++ b/verilog/dv/scan_controller_la/scan_controller_la.gtkw
@@ -1,22 +1,22 @@
[*]
-[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
-[*] Sun Aug 28 03:36:21 2022
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Fri Sep 2 13:07:34 2022
[*]
[dumpfile] "/home/matt/work/asic-workshop/shuttle7/tinytapeout-mpw7/verilog/dv/scan_controller_la/scan_controller_tb.vcd"
-[dumpfile_mtime] "Sun Aug 28 03:33:58 2022"
-[dumpfile_size] 1544765
+[dumpfile_mtime] "Fri Sep 2 13:04:53 2022"
+[dumpfile_size] 5702199
[savefile] "/home/matt/work/asic-workshop/shuttle7/tinytapeout-mpw7/verilog/dv/scan_controller_la/scan_controller_la.gtkw"
[timestart] 0
-[size] 1795 917
+[size] 2149 1120
[pos] -1 -1
-*-29.000000 1829000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-32.000000 3039550000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] scan_controller_tb.
[treeopen] scan_controller_tb.uut.
[treeopen] scan_controller_tb.uut.mprj.
[sst_width] 423
-[signals_width] 261
+[signals_width] 463
[sst_expanded] 1
-[sst_vpaned_height] 254
+[sst_vpaned_height] 323
@28
scan_controller_tb.clk
scan_controller_tb.driver_sel[1:0]
@@ -27,8 +27,8 @@
@800200
-la scan chain
@28
-scan_controller_tb.uut.mprj.scan_controller.la_scan_clk
scan_controller_tb.uut.mprj.scan_controller.la_scan_data_in
+scan_controller_tb.uut.mprj.scan_controller.la_scan_clk_in
scan_controller_tb.uut.mprj.scan_controller.la_scan_data_out
scan_controller_tb.uut.mprj.scan_controller.la_scan_latch_en
scan_controller_tb.uut.mprj.scan_controller.la_scan_select
@@ -36,8 +36,9 @@
-la scan chain
@800200
-scan chain
-@28
-scan_controller_tb.uut.mprj.scan_controller.scan_clk
+@29
+scan_controller_tb.uut.mprj.scan_controller.scan_clk_in
+scan_controller_tb.uut.mprj.scan_controller.scan_clk_out
scan_controller_tb.uut.mprj.scan_controller.scan_data_in
scan_controller_tb.uut.mprj.scan_controller.scan_data_out
scan_controller_tb.uut.mprj.scan_controller.scan_latch_en
diff --git a/verilog/dv/scan_controller_la/scan_controller_tb.v b/verilog/dv/scan_controller_la/scan_controller_tb.v
index 72b5efa..4e9c4f5 100644
--- a/verilog/dv/scan_controller_la/scan_controller_tb.v
+++ b/verilog/dv/scan_controller_la/scan_controller_tb.v
@@ -39,6 +39,7 @@
wire fw_ready = mprj_io[12];
wire fw_done = mprj_io[13];
wire data_rx = mprj_io[14];
+ wire tb_clk = mprj_io[15];
wire [1:0] driver_sel;
assign mprj_io[9:8] = driver_sel;
diff --git a/verilog/dv/scan_controller_la/test_scan_controller.py b/verilog/dv/scan_controller_la/test_scan_controller.py
index 6eadd7e..261b53a 100644
--- a/verilog/dv/scan_controller_la/test_scan_controller.py
+++ b/verilog/dv/scan_controller_la/test_scan_controller.py
@@ -27,14 +27,27 @@
dut.RSTB.value = 1
# wait with a timeout for the project to become active
- await with_timeout(RisingEdge(dut.fw_ready), 350, 'us')
+ await with_timeout(RisingEdge(dut.fw_ready), 550, 'us')
print("firmware ready")
- # wait
- await with_timeout(RisingEdge(dut.fw_done), 2800, 'us')
+ print("waiting for LA to clock the scan chain - warning this will take about 15 minutes")
+ # wait a long time
+ step = 0
+ NUM_IOS=8
+ NUM_DESIGNS=20
+ START_TEST=(NUM_DESIGNS-1)*NUM_IOS
- assert(dut.fw_done == 1)
- assert(dut.data_rx == 1)
+ for i in range(NUM_IOS*NUM_DESIGNS):
+ await with_timeout(FallingEdge(dut.tb_clk), 2, 'ms')
+ print("step {} of {} received data {}".format(step, NUM_IOS*NUM_DESIGNS, dut.data_rx.value))
+ step += 1
+ if i in [START_TEST, START_TEST+1, START_TEST+2, START_TEST+3]:
+ assert dut.data_rx.value == 1
+ elif i in [START_TEST+4, START_TEST+5, START_TEST+6, START_TEST+7]:
+ assert dut.data_rx.value == 0
+
+ await with_timeout(RisingEdge(dut.fw_done), 500, 'us')
+ assert(dut.fw_done.value == 1)
await ClockCycles(dut.clk, 100)
