commit 15217f41152539fb3ef16bde73327f67597c1726
author Peter Birch <peter@lightlogic.co.uk> Fri Oct 07 11:18:04 2022 +0100
committer Peter Birch <peter@lightlogic.co.uk> Fri Oct 07 11:23:06 2022 +0100
tree 133dc597041ccf5a5103d08cdaf7f260f3e44fee
parent 9f7b75e7768ae0b2c90af00639f7c38cdba19258

Fixing some issues with logging

verilog/dv/scan_controller/Makefile

diff --git a/verilog/dv/scan_controller/Makefile b/verilog/dv/scan_controller/Makefile
index 332388c..7aba3ec 100644
--- a/verilog/dv/scan_controller/Makefile
+++ b/verilog/dv/scan_controller/Makefile
@@ -85,6 +85,6 @@
 test_scan_controller: TESTCASE=internal_controller
 test_scan_controller: $(COCOTB_RESULTS_FILE)
 
-.PHONY: test_scan_controller
+.PHONY: test_scan_controller_gl
 test_scan_controller_gl: TESTCASE=internal_controller
 test_scan_controller_gl: $(COCOTB_RESULTS_FILE)

verilog/dv/scan_controller/test_scan_controller.py

diff --git a/verilog/dv/scan_controller/test_scan_controller.py b/verilog/dv/scan_controller/test_scan_controller.py
index 25fc9cd..43fa67d 100644
--- a/verilog/dv/scan_controller/test_scan_controller.py
+++ b/verilog/dv/scan_controller/test_scan_controller.py
@@ -37,7 +37,7 @@
     for i in range(11):
         dut.inputs.value = i
         await FallingEdge(dut.ready)
-        print(i, int(dut.outputs))
+        dut._log.info("cycle %d - output state %d", i, int(dut.outputs))
         if i > 0:
             assert 256 - i == int(dut.outputs)
 
@@ -61,7 +61,7 @@
     for i in range(11):
         dut.inputs.value = i
         await FallingEdge(dut.ready)
-        print(i, int(dut.outputs))
+        dut._log.info("cycle %d - output state %d", i, int(dut.outputs))
         if i > 0:
             assert 256 - i == int(dut.outputs)
 
@@ -71,7 +71,7 @@
     cocotb.fork(clock.start())
 
     dut.reset.value = 1
-    dut.set_clk_div.value = 0   
+    dut.set_clk_div.value = 0
     await ClockCycles(dut.clk, 10)
     dut.reset.value = 0
 
@@ -139,7 +139,7 @@
     for i in range(11):
         dut.inputs.value = i
         await FallingEdge(dut.ready)
-        dut._log.info(i, int(dut.outputs))
+        dut._log.info("cycle %d - output state %d", i, int(dut.outputs))
         if i > 0:
             assert i == int(dut.outputs) + 1
 
@@ -151,7 +151,7 @@
     for i in range(11):
         dut.inputs.value = i
         await FallingEdge(dut.ready)
-        dut._log.info(i, int(dut.outputs))
+        dut._log.info("cycle %d - output state %d", i, int(dut.outputs))
         if i > 0:
             assert 256 - i == int(dut.outputs)
 
@@ -162,6 +162,6 @@
         for i in range(11):
             dut.inputs.value = i
             await FallingEdge(dut.ready)
-            dut._log.info(i, int(dut.outputs))
+            dut._log.info("cycle %d - output state %d", i, int(dut.outputs))
             if i > 0:
                 assert i == int(dut.outputs) + 1