add reram crossbar files
diff --git a/README.md b/README.md
index d7d53a3..b2d3b4c 100644
--- a/README.md
+++ b/README.md
@@ -1,18 +1 @@
-# Caravel Analog User
-
-[](https://opensource.org/licenses/Apache-2.0) [](https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml) [](https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml)
-
----
-
-| :exclamation: Important Note |
-|-----------------------------------------|
-
-## Please fill in your project documentation in this README.md file
-
-
-:warning: | Use this sample project for analog user projects.
-:---: | :---
-
----
-
-Refer to [README](docs/source/index.rst) for this sample project documentation.
+ReRAM 16x16 array characterisation, including forming, incremental set and reset, and parallel analog read for vector-matrix multiplication. All characterisation is fully digitally controlled over the logic analyser.
diff --git a/caravel b/caravel
index 0f16ba8..de98d51 160000
--- a/caravel
+++ b/caravel
@@ -1 +1 @@
-Subproject commit 0f16ba8eaae841a6f122fc0d5837005d3312fd2b
+Subproject commit de98d514aa6c642ef020876a64c4cdb2c9ea9a8a
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index 764b362..fa319e9 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/netgen/.user_analog_project_wrapper.spice.swp b/netgen/.user_analog_project_wrapper.spice.swp
new file mode 100644
index 0000000..f03da2e
--- /dev/null
+++ b/netgen/.user_analog_project_wrapper.spice.swp
Binary files differ
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index c3851a3..6b581ff 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice
@@ -1,336 +1,4557 @@
-* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130B
-.subckt sky130_fd_pr__cap_mim_m3_2_W5U4AW c2_n3079_n3000# m4_n3179_n3100#
-X0 c2_n3079_n3000# m4_n3179_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
+.subckt sky130_fd_sc_hd__and4_4 A B C D VGND VPWR X VNB VPB
+X0 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=1.43e+12p pd=1.286e+07u as=5.4e+11p ps=5.08e+06u w=1e+06u l=150000u
+X1 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_188_47# B a_109_47# VNB sky130_fd_pr__nfet_01v8 ad=2.1775e+11p pd=1.97e+06u as=1.5925e+11p ps=1.79e+06u w=650000u l=150000u
+X3 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VGND D a_285_47# VNB sky130_fd_pr__nfet_01v8 ad=5.5575e+11p pd=5.61e+06u as=2.8275e+11p ps=2.17e+06u w=650000u l=150000u
+X5 VPWR D a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=7e+11p ps=5.4e+06u w=1e+06u l=150000u
+X6 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.51e+11p ps=3.68e+06u w=650000u l=150000u
+X8 VPWR B a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X10 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X11 a_27_47# C VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X13 a_27_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_285_47# C a_188_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X15 a_109_47# A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.69e+11p ps=1.82e+06u w=650000u l=150000u
.ends
-.subckt sky130_fd_sc_hvl__buf_8 A VGND VPWR X VNB VPB
-X0 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X1 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X2 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X3 a_45_443# A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
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-X5 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X6 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X7 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
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-X11 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
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-X13 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X14 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X15 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
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-X21 a_45_443# A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+.subckt sky130_fd_sc_hd__inv_16 A VGND VPWR Y VNB VPB
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+X16 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X17 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
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+X25 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
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+X29 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X30 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
.ends
-.subckt sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ a_n683_n200# a_n189_n297# a_29_n297# a_189_n200#
-+ a_n901_n200# a_247_n297# a_n407_n297# a_465_n297# a_407_n200# a_n625_n297# a_683_n297#
-+ a_625_n200# a_n843_n297# w_n1101_n497# a_843_n200# a_n29_n200# a_n247_n200# a_n465_n200#
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+.subckt decoder_3to8_top Y5 Y6 Y7 IN1 Y4 Y1 Y0 Y3 EN Y2 IN2 IN0 VP VN
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+Xsky130_fd_sc_hd__and4_4_78 IN2 IN1 IN0 EN VN VP Y7 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_67 IN2 IN1 IN0b EN VN VP Y6 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_56 IN2 IN1b IN0 EN VN VP Y5 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_45 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_12 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_23 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_34 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_79 IN2 IN1 IN0 EN VN VP Y7 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_68 IN2 IN1 IN0b EN VN VP Y6 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_57 IN2 IN1b IN0 EN VN VP Y5 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_46 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_35 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_13 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_24 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_69 IN2 IN1 IN0b EN VN VP Y6 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_58 IN2 IN1b IN0 EN VN VP Y5 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_47 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_36 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_25 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_14 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_59 IN2 IN1b IN0 EN VN VP Y5 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_48 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_37 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_26 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_15 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_49 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_38 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_27 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_16 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_39 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_28 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_17 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_29 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_18 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_19 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__inv_16_0 IN0 VN VP IN0b VN VP sky130_fd_sc_hd__inv_16
+Xsky130_fd_sc_hd__inv_16_1 IN1 VN VP IN1b VN VP sky130_fd_sc_hd__inv_16
+Xsky130_fd_sc_hd__and4_4_0 IN2b IN1b IN0b EN VN VP Y0 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__and4_4_1 IN2b IN1b IN0b EN VN VP Y0 VN VP sky130_fd_sc_hd__and4_4
+Xsky130_fd_sc_hd__inv_16_2 IN2 VN VP IN2b VN VP sky130_fd_sc_hd__inv_16
.ends
-.subckt sky130_fd_pr__nfet_g5v0d10v5_TGFUGS a_n792_n200# a_298_n200# a_516_n200# a_734_n200#
-+ w_n962_n458# a_138_n288# a_n298_n288# a_80_n200# a_356_n288# a_n516_n288# a_574_n288#
-+ a_n734_n288# a_n138_n200# a_n356_n200# a_n574_n200# a_n80_n288#
-X0 a_80_n200# a_n80_n288# a_n138_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X1 a_n574_n200# a_n734_n288# a_n792_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X2 a_734_n200# a_574_n288# a_516_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X3 a_298_n200# a_138_n288# a_80_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X4 a_n138_n200# a_n298_n288# a_n356_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X5 a_n356_n200# a_n516_n288# a_n574_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X6 a_516_n200# a_356_n288# a_298_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt top_interconnect WL4 col5_sel A2c latch_high5 row6_sel WL3 latch_high4 A3c
++ m4_556058_405560# WL2 A4c latch_high3 m2_510582_695380# col2_sel B0r power_interconnect_8/m4_556680_101952#
++ WL1 m4_555338_405560# A5c latch_high2 row3_sel B1r WL0 A6c latch_high1 WR SAMPLE
++ B2r A7c latch_high0 B3r A8c A10c power_interconnect_5/m4_555338_13760# row0_sel
++ B4r A9c A11c B5r power_interconnect_7/m4_557302_101232# A12c B6r A13c B7r A14c power_interconnect_6/m4_555960_102672#
++ Vrplus m4_557498_405560# B8r Vcminus A15c B9r m4_556778_405560# RISC_CLK power_interconnect_4/m4_557302_101232#
++ col3_sel row4_sel B10r RSEL1 B11r RSEL0 col0_sel power_interconnect_4/m4_555338_13760#
++ B12r row1_sel B0c B13r power_interconnect_4/m4_555960_102672# B1c m4_556778_499484#
++ B14r A0r RSEL2 B2c B15r A1r B3c Vref_comp power_interconnect_1/m4_556680_102672#
++ A2r m4_557498_499484# B4c power_interconnect_4/m4_556680_101952# A3r m4_556058_604820#
++ B5c A4r vssa1 m4_555338_604820# CSEL1 B6c power_interconnect_6/m4_555338_13760#
++ A5r power_interconnect_5/m4_555960_102672# B7c CSEL0 col4_sel WL15 A6r Vcplus row5_sel
++ B8c WL14 A7r Vgnr EN B9c WL13 A10r A8r power_interconnect_3/m4_557302_101232# col1_sel
++ WL12 A11r A9r Vgpr power_interconnect_1/m4_555960_101952# m4_555338_499484# row2_sel
++ WL11 A12r B10c WL10 A13r power_interconnect_6/m4_556680_101952# power_interconnect_8/m4_557302_101232#
++ power_interconnect_8/m4_555338_13760# WL9 A14r B11c vccd1 m4_557498_604820# power_interconnect_3/m4_555338_13760#
++ WL8 B12c A15r power_interconnect_1/m4_555338_13760# m4_556058_499484# Vref m4_556778_604820#
++ power_interconnect_7/m4_555960_102672# WL7 B13c Vrminus WL6 B14c A0c CSEL2 WL5 B15c
++ A1c VSUBS vdda1 m3_557498_235220# power_interconnect_3/m4_556680_101952#
+Xdecoder_3to8_top_0 col5_sel decoder_3to8_top_0/Y6 decoder_3to8_top_0/Y7 CSEL1 col4_sel
++ col1_sel col0_sel col3_sel EN col2_sel CSEL2 CSEL0 vccd1 VSUBS decoder_3to8_top
+Xdecoder_3to8_top_1 row5_sel row6_sel decoder_3to8_top_1/Y7 RSEL1 row4_sel row1_sel
++ row0_sel row3_sel EN row2_sel RSEL2 RSEL0 vccd1 VSUBS decoder_3to8_top
.ends
-.subckt sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 a_n1806_2500# a_n4122_n2932# a_n5280_2500#
-+ a_2054_n2932# a_896_n2932# a_4756_2500# a_3598_n2932# a_3212_2500# a_n3736_n2932#
-+ a_1668_n2932# a_n1806_n2932# a_5142_n2932# a_896_2500# a_510_n2932# a_n3350_2500#
-+ a_n4508_2500# a_3212_n2932# a_n4894_2500# a_1282_2500# w_n5446_n3098# a_4756_n2932#
-+ a_2826_2500# a_2826_n2932# a_n2192_n2932# a_n1034_2500# a_n2578_2500# a_n1420_2500#
-+ a_n2964_2500# a_n648_n2932# a_n648_2500# a_n5280_n2932# a_n3350_n2932# a_4370_2500#
-+ a_1282_n2932# a_124_n2932# a_n1420_n2932# a_n4894_n2932# a_124_2500# a_n2964_n2932#
-+ a_n4122_2500# a_2054_2500# a_510_2500# a_n4508_n2932# a_4370_n2932# a_3598_2500#
-+ a_3984_2500# a_2440_n2932# a_2440_2500# a_3984_n2932# a_n2192_2500# a_n3736_2500#
-+ a_1668_2500# a_n262_n2932# a_n262_2500# a_n1034_n2932# a_5142_2500# a_n2578_n2932#
-X0 a_n2578_n2932# a_n2578_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X1 a_n1420_n2932# a_n1420_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X2 a_n1806_n2932# a_n1806_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X3 a_3212_n2932# a_3212_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X4 a_3598_n2932# a_3598_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X5 a_n2964_n2932# a_n2964_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X6 a_2826_n2932# a_2826_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X7 a_4370_n2932# a_4370_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X8 a_3984_n2932# a_3984_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X9 a_n262_n2932# a_n262_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X10 a_n3350_n2932# a_n3350_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X11 a_n4122_n2932# a_n4122_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X12 a_n3736_n2932# a_n3736_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X13 a_5142_n2932# a_5142_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X14 a_n4894_n2932# a_n4894_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X15 a_1282_n2932# a_1282_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X16 a_4756_n2932# a_4756_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X17 a_124_n2932# a_124_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X18 a_510_n2932# a_510_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X19 a_896_n2932# a_896_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X20 a_n648_n2932# a_n648_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X21 a_n5280_n2932# a_n5280_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X22 a_n4508_n2932# a_n4508_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X23 a_n1034_n2932# a_n1034_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X24 a_n2192_n2932# a_n2192_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X25 a_2054_n2932# a_2054_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X26 a_1668_n2932# a_1668_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X27 a_2440_n2932# a_2440_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+.subckt sky130_fd_sc_hd__inv_8 A VGND VPWR Y VNB VPB
+X0 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=1.33e+12p pd=1.266e+07u as=1.08e+12p ps=1.016e+07u w=1e+06u l=150000u
+X1 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=7.02e+11p pd=7.36e+06u as=8.645e+11p ps=9.16e+06u w=650000u l=150000u
+X3 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X4 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X7 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X9 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X12 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X13 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X14 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
.ends
-.subckt sky130_fd_pr__pfet_g5v0d10v5_3YBPVB a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt comp_out_sel latch_high latch_high_col vccd1 row_sel vssd1
+Xsky130_fd_sc_hd__inv_8_0 latch_high vssd1 vccd1 sky130_fd_sc_hd__inv_8_0/Y vssd1
++ vccd1 sky130_fd_sc_hd__inv_8
+Xsky130_fd_sc_hd__inv_8_1 row_sel vssd1 vccd1 row_selb vssd1 vccd1 sky130_fd_sc_hd__inv_8
+Xsky130_fd_sc_hd__inv_16_0 row_selb vssd1 vccd1 row_selbuff vssd1 vccd1 sky130_fd_sc_hd__inv_16
+X0 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=1.242e+13p pd=1.1284e+08u as=1.325e+13p ps=1.165e+08u w=1e+06u l=150000u
+X1 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=8.05675e+12p pd=8.199e+07u as=8.59625e+12p ps=8.495e+07u w=650000u l=150000u
+X2 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=5.9e+12p ps=5.18e+07u w=1e+06u l=150000u
+X3 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.835e+12p ps=3.78e+07u w=650000u l=150000u
+X4 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X5 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X6 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X9 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X10 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X11 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X15 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X16 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X18 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X21 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X23 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X25 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X30 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X31 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X33 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X36 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X38 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X39 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X41 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X42 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X45 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X52 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X53 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X54 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X56 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X57 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X62 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X64 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X65 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X66 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X67 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X72 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X75 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X77 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X78 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X80 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X81 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X82 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X83 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X84 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X85 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X86 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X87 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X88 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X89 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X90 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X91 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X92 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X93 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X94 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X95 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X96 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X97 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X98 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X99 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X100 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X101 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X102 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X103 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X104 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X105 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X106 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X107 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X108 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X109 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X110 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X111 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X112 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X113 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X114 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X115 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X116 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X117 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X118 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X119 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X120 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X121 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X122 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X123 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X124 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X125 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X126 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X127 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X128 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X129 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X130 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X131 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X132 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X133 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X134 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X135 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X136 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X137 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X138 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X139 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X140 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X141 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X142 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X143 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X144 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X145 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X146 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X147 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X148 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X149 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X150 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X151 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X152 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X153 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X154 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X155 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X156 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X157 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X158 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X159 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
.ends
-.subckt sky130_fd_sc_hvl__schmittbuf_1 A VGND VPWR X VNB VPB
-X0 X a_117_181# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X1 a_217_207# a_117_181# a_64_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
-X2 VPWR A a_231_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X3 VGND A a_217_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
-X4 a_78_463# VGND VNB sky130_fd_pr__res_generic_nd__hv w=290000u l=1.355e+06u
-X5 a_64_207# VPWR VPB sky130_fd_pr__res_generic_pd__hv w=290000u l=3.11e+06u
-X6 X a_117_181# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X7 a_231_463# A a_117_181# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X8 a_231_463# a_117_181# a_78_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X9 a_217_207# A a_117_181# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
+.subckt x1T1R row WL col body
+X0 row a_100_0# sky130_fd_pr__reram_reram_cell area_ox=1.6e+11p
+X1 a_100_0# WL col body sky130_fd_pr__nfet_g5v0d10v5 ad=4e+11p pd=2.8e+06u as=4e+11p ps=2.8e+06u w=1e+06u l=500000u
.ends
-.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPXE a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt x1T1R_2x2 row0 row1 col0 WL0 col1 body WL1
+X1T1R_0 row1 WL1 col0 body x1T1R
+X1T1R_1 row1 WL1 col1 body x1T1R
+X1T1R_3 row0 WL0 col1 body x1T1R
+X1T1R_2 row0 WL0 col0 body x1T1R
.ends
-.subckt sky130_fd_pr__nfet_g5v0d10v5_PKVMTM w_n308_n458# a_80_n200# a_n138_n200# a_n80_n288#
-X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt x1T1R_16x16 row2 row3 row4 row5 row6 row8 row9 row13 row14 row15 col0 col1
++ col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13 col14 col15 WL5
++ WL6 WL7 WL8 WL13 WL14 row11 row10 WL2 WL4 WL15 WL3 row7 WL0 WL11 WL10 WL9 row1 WL12
++ row12 row0 body WL1
+X1T1R_2x2_0 row0 row1 col0 WL0 col1 body WL1 x1T1R_2x2
+X1T1R_2x2_1 row0 row1 col2 WL0 col3 body WL1 x1T1R_2x2
+X1T1R_2x2_2 row0 row1 col4 WL0 col5 body WL1 x1T1R_2x2
+X1T1R_2x2_3 row0 row1 col6 WL0 col7 body WL1 x1T1R_2x2
+X1T1R_2x2_4 row0 row1 col8 WL0 col9 body WL1 x1T1R_2x2
+X1T1R_2x2_5 row0 row1 col10 WL0 col11 body WL1 x1T1R_2x2
+X1T1R_2x2_6 row0 row1 col12 WL0 col13 body WL1 x1T1R_2x2
+X1T1R_2x2_7 row0 row1 col14 WL0 col15 body WL1 x1T1R_2x2
+X1T1R_2x2_8 row2 row3 col0 WL2 col1 body WL3 x1T1R_2x2
+X1T1R_2x2_9 row2 row3 col2 WL2 col3 body WL3 x1T1R_2x2
+X1T1R_2x2_60 row14 row15 col8 WL14 col9 body WL15 x1T1R_2x2
+X1T1R_2x2_62 row14 row15 col12 WL14 col13 body WL15 x1T1R_2x2
+X1T1R_2x2_61 row14 row15 col10 WL14 col11 body WL15 x1T1R_2x2
+X1T1R_2x2_51 row12 row13 col6 WL12 col7 body WL13 x1T1R_2x2
+X1T1R_2x2_50 row12 row13 col4 WL12 col5 body WL13 x1T1R_2x2
+X1T1R_2x2_40 row10 row11 col0 WL10 col1 body WL11 x1T1R_2x2
+X1T1R_2x2_63 row14 row15 col14 WL14 col15 body WL15 x1T1R_2x2
+X1T1R_2x2_52 row12 row13 col8 WL12 col9 body WL13 x1T1R_2x2
+X1T1R_2x2_41 row10 row11 col2 WL10 col3 body WL11 x1T1R_2x2
+X1T1R_2x2_30 row6 row7 col2 WL6 col3 body WL7 x1T1R_2x2
+X1T1R_2x2_53 row12 row13 col10 WL12 col11 body WL13 x1T1R_2x2
+X1T1R_2x2_42 row10 row11 col4 WL10 col5 body WL11 x1T1R_2x2
+X1T1R_2x2_31 row6 row7 col0 WL6 col1 body WL7 x1T1R_2x2
+X1T1R_2x2_20 row4 row5 col8 WL4 col9 body WL5 x1T1R_2x2
+X1T1R_2x2_54 row12 row13 col12 WL12 col13 body WL13 x1T1R_2x2
+X1T1R_2x2_43 row10 row11 col6 WL10 col7 body WL11 x1T1R_2x2
+X1T1R_2x2_32 row8 row9 col0 WL8 col1 body WL9 x1T1R_2x2
+X1T1R_2x2_21 row4 row5 col10 WL4 col11 body WL5 x1T1R_2x2
+X1T1R_2x2_10 row2 row3 col4 WL2 col5 body WL3 x1T1R_2x2
+X1T1R_2x2_55 row12 row13 col14 WL12 col15 body WL13 x1T1R_2x2
+X1T1R_2x2_44 row10 row11 col8 WL10 col9 body WL11 x1T1R_2x2
+X1T1R_2x2_33 row8 row9 col2 WL8 col3 body WL9 x1T1R_2x2
+X1T1R_2x2_22 row4 row5 col12 WL4 col13 body WL5 x1T1R_2x2
+X1T1R_2x2_11 row2 row3 col6 WL2 col7 body WL3 x1T1R_2x2
+X1T1R_2x2_56 row14 row15 col0 WL14 col1 body WL15 x1T1R_2x2
+X1T1R_2x2_45 row10 row11 col10 WL10 col11 body WL11 x1T1R_2x2
+X1T1R_2x2_34 row8 row9 col4 WL8 col5 body WL9 x1T1R_2x2
+X1T1R_2x2_23 row4 row5 col14 WL4 col15 body WL5 x1T1R_2x2
+X1T1R_2x2_12 row2 row3 col8 WL2 col9 body WL3 x1T1R_2x2
+X1T1R_2x2_57 row14 row15 col2 WL14 col3 body WL15 x1T1R_2x2
+X1T1R_2x2_46 row10 row11 col12 WL10 col13 body WL11 x1T1R_2x2
+X1T1R_2x2_35 row8 row9 col6 WL8 col7 body WL9 x1T1R_2x2
+X1T1R_2x2_24 row6 row7 col14 WL6 col15 body WL7 x1T1R_2x2
+X1T1R_2x2_13 row2 row3 col10 WL2 col11 body WL3 x1T1R_2x2
+X1T1R_2x2_58 row14 row15 col4 WL14 col5 body WL15 x1T1R_2x2
+X1T1R_2x2_47 row10 row11 col14 WL10 col15 body WL11 x1T1R_2x2
+X1T1R_2x2_36 row8 row9 col8 WL8 col9 body WL9 x1T1R_2x2
+X1T1R_2x2_25 row6 row7 col12 WL6 col13 body WL7 x1T1R_2x2
+X1T1R_2x2_14 row2 row3 col12 WL2 col13 body WL3 x1T1R_2x2
+X1T1R_2x2_59 row14 row15 col6 WL14 col7 body WL15 x1T1R_2x2
+X1T1R_2x2_48 row12 row13 col0 WL12 col1 body WL13 x1T1R_2x2
+X1T1R_2x2_49 row12 row13 col2 WL12 col3 body WL13 x1T1R_2x2
+X1T1R_2x2_38 row8 row9 col12 WL8 col13 body WL9 x1T1R_2x2
+X1T1R_2x2_37 row8 row9 col10 WL8 col11 body WL9 x1T1R_2x2
+X1T1R_2x2_26 row6 row7 col10 WL6 col11 body WL7 x1T1R_2x2
+X1T1R_2x2_27 row6 row7 col8 WL6 col9 body WL7 x1T1R_2x2
+X1T1R_2x2_16 row4 row5 col0 WL4 col1 body WL5 x1T1R_2x2
+X1T1R_2x2_15 row2 row3 col14 WL2 col15 body WL3 x1T1R_2x2
+X1T1R_2x2_39 row8 row9 col14 WL8 col15 body WL9 x1T1R_2x2
+X1T1R_2x2_28 row6 row7 col6 WL6 col7 body WL7 x1T1R_2x2
+X1T1R_2x2_17 row4 row5 col2 WL4 col3 body WL5 x1T1R_2x2
+X1T1R_2x2_29 row6 row7 col4 WL6 col5 body WL7 x1T1R_2x2
+X1T1R_2x2_18 row4 row5 col4 WL4 col5 body WL5 x1T1R_2x2
+X1T1R_2x2_19 row4 row5 col6 WL4 col7 body WL5 x1T1R_2x2
.ends
-.subckt sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC w_n308_n458# a_80_n200# a_n138_n200# a_n80_n288#
-X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt sky130_fd_sc_hd__inv_2 A VGND VPWR Y VNB VPB
+X0 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=2.7e+11p pd=2.54e+06u as=5.2e+11p ps=5.04e+06u w=1e+06u l=150000u
+X1 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=3.38e+11p pd=3.64e+06u as=1.755e+11p ps=1.84e+06u w=650000u l=150000u
+X2 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X3 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
.ends
-.subckt sky130_fd_pr__cap_mim_m3_1_WRT4AW c1_n3036_n3000# m3_n3136_n3100#
-X0 c1_n3036_n3000# m3_n3136_n3100# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=3e+07u
+.subckt sky130_fd_sc_hd__and2_4 A B VGND VPWR X VNB VPB
+X0 VPWR B a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=1.185e+12p pd=1.037e+07u as=2.8e+11p ps=2.56e+06u w=1e+06u l=150000u
+X1 a_27_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=3.64e+11p pd=3.72e+06u as=6.435e+11p ps=5.88e+06u w=650000u l=150000u
+X3 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=5.6e+11p ps=5.12e+06u w=1e+06u l=150000u
+X4 VGND B a_110_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.365e+11p ps=1.72e+06u w=650000u l=150000u
+X5 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_110_47# A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.7225e+11p ps=1.83e+06u w=650000u l=150000u
+X7 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X9 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X10 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
.ends
-.subckt sky130_fd_pr__pfet_g5v0d10v5_YEUEBV a_n792_n200# a_138_n297# a_n298_n297#
-+ a_298_n200# a_356_n297# a_n516_n297# a_574_n297# a_516_n200# a_n734_n297# a_734_n200#
-+ a_n80_n297# a_80_n200# a_n138_n200# a_n356_n200# a_n574_n200# w_n992_n497#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X1 a_n574_n200# a_n734_n297# a_n792_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X2 a_734_n200# a_574_n297# a_516_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X3 a_298_n200# a_138_n297# a_80_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X4 a_n138_n200# a_n298_n297# a_n356_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X5 a_n356_n200# a_n516_n297# a_n574_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X6 a_516_n200# a_356_n297# a_298_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt and_pair SEL A B OUT_A OUT_B vssd1 vccd1
+X0 OUT_A a_n932_n2764# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=4e+11p pd=2.8e+06u as=4.8e+12p ps=3.36e+07u w=1e+06u l=150000u
+X1 vccd1 A a_n932_n2764# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=8e+11p ps=5.6e+06u w=1e+06u l=150000u
+X2 a_n2012_n2764# B a_n2144_n2764# vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=5.1e+11p ps=3.02e+06u w=1e+06u l=150000u
+X3 vccd1 a_n2012_n2764# OUT_B vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4e+11p ps=2.8e+06u w=1e+06u l=150000u
+X4 a_n2012_n2764# B vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=8e+11p pd=5.6e+06u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n2012_n2764# SEL vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n932_n2764# SEL vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 vssd1 SEL a_n134_n2764# vssd1 sky130_fd_pr__nfet_01v8 ad=1.6e+12p pd=1.12e+07u as=5.1e+11p ps=3.02e+06u w=1e+06u l=150000u
+X8 vccd1 a_n932_n2764# OUT_A vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 vccd1 B a_n2012_n2764# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_n2144_n2764# SEL vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_n932_n2764# A vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 vccd1 SEL a_n2012_n2764# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 OUT_A a_n932_n2764# vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=0p ps=0u w=1e+06u l=150000u
+X14 OUT_B a_n2012_n2764# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 vssd1 a_n2012_n2764# OUT_B vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=4e+11p ps=2.8e+06u w=1e+06u l=150000u
+X16 vccd1 SEL a_n932_n2764# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_n134_n2764# A a_n932_n2764# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=4e+11p ps=2.8e+06u w=1e+06u l=150000u
.ends
-.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPBG a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt col_driver_x50 Vcminus Vref Vcplus SWrefb SWref SWcminus SWcplus col VP VN
+X0 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=1.26e+13p pd=8.12e+07u as=2.34e+13p ps=1.508e+08u w=1e+06u l=500000u
+X1 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=1.26e+13p pd=8.12e+07u as=0p ps=0u w=1e+06u l=500000u
+X2 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X3 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X4 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=6.3e+12p pd=4.06e+07u as=1.26e+13p ps=8.12e+07u w=1e+06u l=500000u
+X5 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X6 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X7 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=6.3e+12p pd=4.06e+07u as=0p ps=0u w=1e+06u l=500000u
+X8 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X9 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X10 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X11 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X12 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X13 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X14 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X15 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X16 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X17 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X18 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X19 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X20 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X21 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X22 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X23 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X24 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X25 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X26 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X27 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X28 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X29 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X30 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X31 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X32 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X33 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X34 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X35 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X36 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X37 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X38 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X39 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X40 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X41 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X42 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X43 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X44 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X45 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X46 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X47 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X48 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X49 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X50 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X51 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X52 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X53 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X54 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X55 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X56 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X57 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X58 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X59 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X60 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X61 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X62 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X63 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X64 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X65 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X66 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X67 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X68 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X69 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X70 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X71 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X72 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X73 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X74 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X75 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X76 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X77 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X78 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X79 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X80 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X81 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X82 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X83 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X84 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X85 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X86 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X87 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X88 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X89 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X90 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X91 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X92 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X93 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X94 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X95 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X96 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X97 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X98 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X99 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X100 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X101 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X102 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X103 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X104 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X105 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X106 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X107 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X108 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X109 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X110 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X111 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X112 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X113 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X114 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X115 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X116 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X117 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X118 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X119 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X120 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X121 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X122 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X123 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X124 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X125 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X126 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X127 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X128 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X129 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X130 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X131 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X132 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X133 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X134 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X135 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X136 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X137 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X138 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X139 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X140 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X141 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X142 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X143 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X144 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X145 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X146 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X147 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X148 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X149 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
.ends
-.subckt sky130_fd_sc_hvl__inv_8 A VGND VPWR Y VNB VPB
-X0 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X1 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X2 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X3 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X4 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X5 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X6 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X7 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X8 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X9 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X10 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X11 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X12 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X13 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X14 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X15 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+.subckt level_up_shifter_x4 in outb out vssd1 vccd1 vdda1
+X0 vssd1 in outb vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=2.25e+12p pd=1.45e+07u as=2.25e+12p ps=1.45e+07u w=1e+06u l=500000u
+X1 vdda1 outb out vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=1.8e+12p pd=1.16e+07u as=9e+11p ps=5.8e+06u w=1e+06u l=500000u
+X2 a_0_n3806# in vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=8e+11p pd=5.6e+06u as=8e+11p ps=5.6e+06u w=1e+06u l=150000u
+X3 vdda1 out outb vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=9e+11p ps=5.8e+06u w=1e+06u l=500000u
+X4 out a_0_n3806# vssd1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=1.8e+12p pd=1.16e+07u as=0p ps=0u w=1e+06u l=500000u
+X5 out in vdda1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=2.95e+12p ps=1.79e+07u w=1e+06u l=500000u
+X6 outb a_0_n3806# vdda1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X7 vdda1 in out vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X8 outb in vssd1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X9 out outb vdda1 vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X10 outb out vdda1 vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X11 vccd1 in a_0_n3806# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 vdda1 outb out vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X13 vssd1 a_0_n3806# out vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X14 vdda1 a_0_n3806# outb vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X15 out a_0_n3806# vssd1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X16 out in vdda1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X17 vssd1 in outb vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X18 vccd1 in a_0_n3806# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_0_n3806# in vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=4e+11p ps=2.8e+06u w=1e+06u l=150000u
+X20 vdda1 out outb vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X21 outb a_0_n3806# vdda1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X22 outb in vssd1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X23 vssd1 a_0_n3806# out vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X24 vdda1 in out vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X25 vdda1 a_0_n3806# outb vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
.ends
-.subckt example_por vdd3v3 vss porb_h por_l porb_l vdd1v8
-Xsky130_fd_pr__cap_mim_m3_2_W5U4AW_0 vss sky130_fd_sc_hvl__schmittbuf_1_0/A sky130_fd_pr__cap_mim_m3_2_W5U4AW
-Xsky130_fd_sc_hvl__buf_8_1 sky130_fd_sc_hvl__inv_8_0/A vss vdd1v8 porb_l vss vdd1v8
-+ sky130_fd_sc_hvl__buf_8
-Xsky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0 m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653#
-+ vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653#
-+ m1_502_7653# vdd3v3 vdd3v3 vdd3v3 m1_502_7653# vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ
-Xsky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0 m1_721_6815# vss m1_721_6815# vss vss m1_721_6815#
-+ m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# vss
-+ m1_721_6815# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_TGFUGS
-Xsky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0 li_3322_5813# li_1391_165# vss li_7567_165#
-+ li_6023_165# vdd3v3 li_9111_165# li_8726_5813# li_1391_165# li_6795_165# li_3707_165#
-+ vss li_6410_5813# li_6023_165# li_1778_5813# li_1006_5813# li_8339_165# vss li_6410_5813#
-+ vss li_9883_165# li_7954_5813# li_8339_165# li_2935_165# li_4094_5813# li_2550_5813#
-+ li_4094_5813# li_2550_5813# li_4479_165# li_4866_5813# vss li_2163_165# li_9498_5813#
-+ li_6795_165# li_5251_165# li_3707_165# li_619_165# li_5638_5813# li_2163_165# li_1006_5813#
-+ li_7182_5813# li_5638_5813# li_619_165# li_9883_165# li_8726_5813# li_9498_5813#
-+ li_7567_165# li_7954_5813# li_9111_165# li_3322_5813# li_1778_5813# li_7182_5813#
-+ li_5251_165# li_4866_5813# li_4479_165# vss li_2935_165# sky130_fd_pr__res_xhigh_po_0p69_S5N9F3
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0 m1_185_6573# m1_721_6815# vdd3v3 m1_2993_7658#
-+ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_sc_hvl__schmittbuf_1_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss vdd3v3 sky130_fd_sc_hvl__inv_8_0/A
-+ vss vdd3v3 sky130_fd_sc_hvl__schmittbuf_1
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1 m1_2756_6573# m1_4283_8081# vdd3v3 m1_2756_6573#
-+ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2 m1_2756_6573# sky130_fd_sc_hvl__schmittbuf_1_0/A
-+ vdd3v3 m1_6249_7690# sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3 m1_185_6573# m1_502_7653# vdd3v3 m1_185_6573#
-+ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0 m1_4283_8081# m1_6249_7690# vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YUHPXE
-Xsky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0 vss m1_2756_6573# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_PKVMTM
-Xsky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1 vss m1_185_6573# vss li_2550_5813# sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC
-Xsky130_fd_pr__cap_mim_m3_1_WRT4AW_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss sky130_fd_pr__cap_mim_m3_1_WRT4AW
-Xsky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0 vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081#
-+ m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081#
-+ vdd3v3 m1_4283_8081# vdd3v3 m1_4283_8081# vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YEUEBV
-Xsky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0 m1_502_7653# m1_2993_7658# vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YUHPBG
-Xsky130_fd_sc_hvl__inv_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vdd1v8 por_l vss vdd1v8
-+ sky130_fd_sc_hvl__inv_8
-Xsky130_fd_sc_hvl__buf_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vdd3v3 porb_h vss vdd3v3
-+ sky130_fd_sc_hvl__buf_8
+.subckt level_up_shifter_drivers_x4 B B_1.8 A_1.8 Ab_1.8 Bb_1.8 vccd1 vdda1 A vssd1
+Xlevel_up_shifter_x4_0 B Bb_1.8 B_1.8 vssd1 vccd1 vdda1 level_up_shifter_x4
+Xlevel_up_shifter_x4_1 A Ab_1.8 A_1.8 vssd1 vccd1 vdda1 level_up_shifter_x4
.ends
-.subckt user_analog_proj_example example_por_0/por_l example_por_1/por_l example_por_1/vdd3v3
-+ example_por_1/porb_l example_por_0/vdd3v3 example_por_1/porb_h example_por_0/porb_l
-+ example_por_0/porb_h VSUBS example_por_0/vdd1v8 example_por_1/vdd1v8
-Xexample_por_0 example_por_0/vdd3v3 VSUBS example_por_0/porb_h example_por_0/por_l
-+ example_por_0/porb_l example_por_0/vdd1v8 example_por
-Xexample_por_1 example_por_1/vdd3v3 VSUBS example_por_1/porb_h example_por_1/por_l
-+ example_por_1/porb_l example_por_1/vdd1v8 example_por
+.subckt decoder2to4_x6 B Bb A Ab A1b A2 A0b A0 VP VN
+X0 A2 a_n20_n174# VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=9e+11p pd=5.8e+06u as=7.18e+12p ps=4.636e+07u w=1e+06u l=500000u
+X1 VN Ab a_100_n2034# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=2.25e+12p ps=1.45e+07u w=1e+06u l=500000u
+X2 A0b A0 VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=1.35e+12p pd=8.7e+06u as=1.394e+13p ps=8.988e+07u w=1e+06u l=500000u
+X3 VP a_n20_2180# A0 VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=1.35e+12p ps=8.7e+06u w=1e+06u l=500000u
+X4 VN a_n20_n174# A2 VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X5 a_n20_2180# Ab VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=3.15e+12p pd=2.03e+07u as=0p ps=0u w=1e+06u l=500000u
+X6 a_n20_2180# Bb a_100_n9284# VN sky130_fd_pr__nfet_g5v0d10v5 ad=1.34e+12p pd=8.68e+06u as=1.8e+12p ps=1.16e+07u w=1e+06u l=500000u
+X7 a_100_n9284# Ab VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X8 A1b Ab VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=2.7e+12p pd=1.74e+07u as=0p ps=0u w=1e+06u l=500000u
+X9 A0b A0 VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X10 a_n20_2180# Bb VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X11 a_100_n9284# Bb a_n20_2180# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X12 VP Bb a_n20_n174# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=3.15e+12p ps=2.03e+07u w=1e+06u l=500000u
+X13 A0b A0 VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=9e+11p pd=5.8e+06u as=0p ps=0u w=1e+06u l=500000u
+X14 VP Ab a_n20_2180# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X15 a_n20_2180# Bb VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X16 VN a_n20_2180# A0 VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=9e+11p ps=5.8e+06u w=1e+06u l=500000u
+X17 a_n20_n174# Bb VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X18 VP a_n20_2180# A0 VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X19 a_100_n2034# B A1b VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=9e+11p ps=5.8e+06u w=1e+06u l=500000u
+X20 A1b B VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X21 a_n20_n174# Bb a_100_n11182# VN sky130_fd_pr__nfet_g5v0d10v5 ad=1.34e+12p pd=8.68e+06u as=2.25e+12p ps=1.45e+07u w=1e+06u l=500000u
+X22 a_n20_n174# Bb a_100_n11182# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X23 a_n20_n174# A VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X24 VP a_n20_n174# A2 VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=1.8e+12p ps=1.16e+07u w=1e+06u l=500000u
+X25 A1b B VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X26 A0 a_n20_2180# VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X27 VN Ab a_100_n9284# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X28 A2 a_n20_n174# VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X29 A2 a_n20_n174# VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X30 a_100_n2034# Ab VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X31 A1b B a_100_n2034# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X32 VP A a_n20_n174# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X33 VP B A1b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X34 VP Ab a_n20_2180# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X35 a_n20_2180# Bb a_100_n9284# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X36 VP A0 A0b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X37 VP Ab A1b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X38 a_n20_n174# Bb VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X39 A0b A0 VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X40 a_n20_2180# Ab VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X41 A1b Ab VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X42 VN A0 A0b VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X43 a_n20_2180# Bb VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X44 VP Bb a_n20_2180# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X45 VP Bb a_n20_2180# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X46 VN A a_100_n11182# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X47 A0 a_n20_2180# VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X48 VP Bb a_n20_n174# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X49 A0 a_n20_2180# VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X50 VN Ab a_100_n2034# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X51 VP B A1b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X52 VP A a_n20_n174# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X53 a_100_n11182# A VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X54 VP a_n20_2180# A0 VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X55 VN a_n20_2180# A0 VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X56 VP a_n20_n174# A2 VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X57 a_100_n2034# B A1b VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X58 a_100_n9284# Ab VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X59 VN A a_100_n11182# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X60 a_n20_n174# A VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X61 a_n20_n174# A VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X62 A1b B VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X63 A1b Ab VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X64 a_n20_2180# Ab VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X65 VP A0 A0b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X66 VP Ab a_n20_2180# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X67 a_100_n9284# Bb a_n20_2180# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X68 VP Ab A1b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X69 VP A0 A0b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X70 A0b A0 VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X71 VP a_n20_n174# A2 VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X72 VP Bb a_n20_2180# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X73 a_n20_n174# Bb VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X74 VN A0 A0b VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X75 A0 a_n20_2180# VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X76 VN a_n20_n174# A2 VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X77 VP Bb a_n20_n174# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X78 A0 a_n20_2180# VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X79 A1b B a_100_n2034# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X80 VP B A1b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X81 a_100_n11182# Bb a_n20_n174# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X82 a_100_n11182# Bb a_n20_n174# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X83 VP A a_n20_n174# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X84 A2 a_n20_n174# VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X85 a_100_n2034# Ab VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X86 VN Ab a_100_n9284# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X87 a_100_n11182# A VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X88 A2 a_n20_n174# VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X89 VP Ab A1b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+.ends
+
+.subckt col_driver_big Vcplus LA_B LA_A vccd1 Vref SEL col decoder2to4_x6_0/A2 decoder2to4_x6_0/A0
++ decoder2to4_x6_0/A1b Vcminus vssd1 vdda1
+Xand_pair_0 SEL LA_A LA_B and_pair_0/OUT_A and_pair_0/OUT_B vssd1 vccd1 and_pair
+Xcol_driver_x50_0 Vcminus Vref Vcplus decoder2to4_x6_0/A0b decoder2to4_x6_0/A0 decoder2to4_x6_0/A2
++ decoder2to4_x6_0/A1b col vdda1 vssd1 col_driver_x50
+Xlevel_up_shifter_drivers_x4_0 and_pair_0/OUT_B decoder2to4_x6_0/B decoder2to4_x6_0/A
++ decoder2to4_x6_0/Ab decoder2to4_x6_0/Bb vccd1 vdda1 and_pair_0/OUT_A vssd1 level_up_shifter_drivers_x4
+Xdecoder2to4_x6_0 decoder2to4_x6_0/B decoder2to4_x6_0/Bb decoder2to4_x6_0/A decoder2to4_x6_0/Ab
++ decoder2to4_x6_0/A1b decoder2to4_x6_0/A2 decoder2to4_x6_0/A0b decoder2to4_x6_0/A0
++ vdda1 vssd1 decoder2to4_x6
+.ends
+
+.subckt col_drivers_1x16 A0 A15 vdda1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14
++ B0 B1 B2 B3 B4 B5 B6 B8 B9 B10 B11 B12 B13 B14 B15 SEL col0 col2 col3 col1 col4
++ col5 col6 col7 col8 col9 col10 col11 col12 col13 col14 col15 col_driver_big_14/decoder2to4_x6_0/A1b
++ col_driver_big_14/decoder2to4_x6_0/A2 col_driver_big_14/decoder2to4_x6_0/A0 Vcminus
++ Vcplus Vref B7 vccd1 vssd1
+Xcol_driver_big_0 Vcplus B0 A0 vccd1 Vref SEL col0 col_driver_big_0/decoder2to4_x6_0/A2
++ col_driver_big_0/decoder2to4_x6_0/A0 col_driver_big_0/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_1 Vcplus B1 A1 vccd1 Vref SEL col1 col_driver_big_1/decoder2to4_x6_0/A2
++ col_driver_big_1/decoder2to4_x6_0/A0 col_driver_big_1/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_2 Vcplus B3 A3 vccd1 Vref SEL col3 col_driver_big_2/decoder2to4_x6_0/A2
++ col_driver_big_2/decoder2to4_x6_0/A0 col_driver_big_2/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_3 Vcplus B2 A2 vccd1 Vref SEL col2 col_driver_big_3/decoder2to4_x6_0/A2
++ col_driver_big_3/decoder2to4_x6_0/A0 col_driver_big_3/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_4 Vcplus B5 A5 vccd1 Vref SEL col5 col_driver_big_4/decoder2to4_x6_0/A2
++ col_driver_big_4/decoder2to4_x6_0/A0 col_driver_big_4/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_5 Vcplus B4 A4 vccd1 Vref SEL col4 col_driver_big_5/decoder2to4_x6_0/A2
++ col_driver_big_5/decoder2to4_x6_0/A0 col_driver_big_5/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_6 Vcplus B7 A7 vccd1 Vref SEL col7 col_driver_big_6/decoder2to4_x6_0/A2
++ col_driver_big_6/decoder2to4_x6_0/A0 col_driver_big_6/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_7 Vcplus B6 A6 vccd1 Vref SEL col6 col_driver_big_7/decoder2to4_x6_0/A2
++ col_driver_big_7/decoder2to4_x6_0/A0 col_driver_big_7/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_10 Vcplus B11 A11 vccd1 Vref SEL col11 col_driver_big_10/decoder2to4_x6_0/A2
++ col_driver_big_10/decoder2to4_x6_0/A0 col_driver_big_10/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_8 Vcplus B9 A9 vccd1 Vref SEL col9 col_driver_big_8/decoder2to4_x6_0/A2
++ col_driver_big_8/decoder2to4_x6_0/A0 col_driver_big_8/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_9 Vcplus B8 A8 vccd1 Vref SEL col8 col_driver_big_9/decoder2to4_x6_0/A2
++ col_driver_big_9/decoder2to4_x6_0/A0 col_driver_big_9/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_11 Vcplus B10 A10 vccd1 Vref SEL col10 col_driver_big_11/decoder2to4_x6_0/A2
++ col_driver_big_11/decoder2to4_x6_0/A0 col_driver_big_11/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_12 Vcplus B13 A13 vccd1 Vref SEL col13 col_driver_big_12/decoder2to4_x6_0/A2
++ col_driver_big_12/decoder2to4_x6_0/A0 col_driver_big_12/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_13 Vcplus B12 A12 vccd1 Vref SEL col12 col_driver_big_13/decoder2to4_x6_0/A2
++ col_driver_big_13/decoder2to4_x6_0/A0 col_driver_big_13/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_14 Vcplus B15 A15 vccd1 Vref SEL col15 col_driver_big_14/decoder2to4_x6_0/A2
++ col_driver_big_14/decoder2to4_x6_0/A0 col_driver_big_14/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+Xcol_driver_big_15 Vcplus B14 A14 vccd1 Vref SEL col14 col_driver_big_15/decoder2to4_x6_0/A2
++ col_driver_big_15/decoder2to4_x6_0/A0 col_driver_big_15/decoder2to4_x6_0/A1b Vcminus
++ vssd1 vdda1 col_driver_big
+.ends
+
+.subckt and_level_up_shifter_x4 SEL vdda1 outb out in vssd1 vccd1
+Xlevel_up_shifter_x4_0 level_up_shifter_x4_0/in outb out vssd1 vccd1 vdda1 level_up_shifter_x4
+X0 vccd1 SEL a_n2010_n2765# vccd1 sky130_fd_pr__pfet_01v8 ad=2.40003e+12p pd=1.6805e+07u as=8e+11p ps=5.6e+06u w=1e+06u l=150000u
+X1 level_up_shifter_x4_0/in a_n2010_n2765# vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=1.2e+12p ps=8.4e+06u w=1e+06u l=150000u
+X2 a_n2010_n2765# in a_n2142_n2765# vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=5.1e+11p ps=3.02e+06u w=1e+06u l=150000u
+X3 a_n2010_n2765# in vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 level_up_shifter_x4_0/in a_n2010_n2765# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=4e+11p pd=2.8e+06u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n2142_n2765# SEL vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n2010_n2765# SEL vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 vccd1 a_n2010_n2765# level_up_shifter_x4_0/in vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 vccd1 in a_n2010_n2765# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt level_up_shifter_2x outb in out vssd1 vccd1 vdda1
+X0 out a_195_n2770# vssd1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=9e+11p pd=5.8e+06u as=1.35e+12p ps=8.7e+06u w=1e+06u l=500000u
+X1 vssd1 a_195_n2770# out vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X2 outb in vssd1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=9e+11p pd=5.8e+06u as=0p ps=0u w=1e+06u l=500000u
+X3 outb a_195_n2770# vdda1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=2.05e+12p ps=1.21e+07u w=1e+06u l=500000u
+X4 vdda1 a_195_n2770# outb vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X5 out in vdda1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X6 a_195_n2770# in vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=4e+11p ps=2.8e+06u w=1e+06u l=150000u
+X7 vdda1 in out vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X8 outb out vdda1 vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=4.5e+11p pd=2.9e+06u as=1.35e+12p ps=8.7e+06u w=1e+06u l=500000u
+X9 vdda1 out outb vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X10 out outb vdda1 vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=4.5e+11p pd=2.9e+06u as=0p ps=0u w=1e+06u l=500000u
+X11 vdda1 outb out vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X12 vccd1 in a_195_n2770# vccd1 sky130_fd_pr__pfet_01v8 ad=4e+11p pd=2.8e+06u as=4e+11p ps=2.8e+06u w=1e+06u l=150000u
+X13 vssd1 in outb vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+.ends
+
+.subckt WL_driver SEL WL WL_out vdda1 vssd1 vccd1
+Xlevel_up_shifter_2x_0 level_up_shifter_2x_0/outb level_up_shifter_2x_0/in WL_out
++ vssd1 vccd1 vdda1 level_up_shifter_2x
+X0 vccd1 SEL a_n2010_n2765# vccd1 sky130_fd_pr__pfet_01v8 ad=4.00025e+11p pd=2.805e+06u as=8e+11p ps=5.6e+06u w=1e+06u l=150000u
+X1 level_up_shifter_2x_0/in a_n2010_n2765# vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=1.2e+12p ps=8.4e+06u w=1e+06u l=150000u
+X2 a_n2010_n2765# WL a_n2142_n2765# vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=5.1e+11p ps=3.02e+06u w=1e+06u l=150000u
+X3 a_n2010_n2765# WL vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 level_up_shifter_2x_0/in a_n2010_n2765# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=4e+11p pd=2.8e+06u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n2142_n2765# SEL vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n2010_n2765# SEL vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 vccd1 a_n2010_n2765# level_up_shifter_2x_0/in vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 vccd1 WL a_n2010_n2765# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt WL_drivers_16x1 SEL vccd1 vdda1 WL15 WL14 WL13 WL12 WL11 WL10 WL9 WL8 WL7
++ WL6 WL5 WL4 WL3 WL2 WL1 WL0 WL_out15 WL_out14 WL_out13 WL_out12 WL_out11 WL_out10
++ WL_out9 WL_out8 WL_out7 WL_out6 WL_out5 WL_out4 WL_out3 WL_out2 WL_out1 WL_out0
++ vssd1
+XWL_driver_0[0] SEL WL15 WL_out15 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[1] SEL WL14 WL_out14 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[2] SEL WL13 WL_out13 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[3] SEL WL12 WL_out12 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[4] SEL WL11 WL_out11 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[5] SEL WL10 WL_out10 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[6] SEL WL9 WL_out9 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[7] SEL WL8 WL_out8 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[8] SEL WL7 WL_out7 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[9] SEL WL6 WL_out6 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[10] SEL WL5 WL_out5 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[11] SEL WL4 WL_out4 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[12] SEL WL3 WL_out3 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[13] SEL WL2 WL_out2 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[14] SEL WL1 WL_out1 vdda1 vssd1 vccd1 WL_driver
+XWL_driver_0[15] SEL WL0 WL_out0 vdda1 vssd1 vccd1 WL_driver
+.ends
+
+.subckt row_driver_x30 SWref SWrminus row vgpr Vrplus Vsample SAMPLEb SAMPLE WR Vref
++ WRb SWrefb SWrplus Vgnr Vrminus VP VN
+X0 a_13042_n4118# Vgnr Vrminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=7.65e+12p pd=4.93e+07u as=3.6e+12p ps=2.32e+07u w=1e+06u l=500000u
+X1 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=7.2e+12p pd=4.64e+07u as=1.485e+13p ps=9.57e+07u w=1e+06u l=500000u
+X2 Vref WR a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=2.7e+12p pd=1.74e+07u as=8.1e+12p ps=5.22e+07u w=1e+06u l=500000u
+X3 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X4 a_13042_n4118# Vgnr Vrminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X5 Vref WRb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=5.38e+12p pd=3.476e+07u as=1.755e+13p ps=1.131e+08u w=1e+06u l=500000u
+X6 Vref WRb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X7 Vref WR a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X8 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=1.301e+13p ps=8.402e+07u w=1e+06u l=500000u
+X9 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=5.38e+12p pd=3.476e+07u as=0p ps=0u w=1e+06u l=500000u
+X10 a_19432_n4118# WR Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X11 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X12 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X13 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X14 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X15 Vrminus Vgnr a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X16 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X17 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X18 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X19 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X20 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X21 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X22 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X23 a_19432_n4118# SWref row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=6.3e+12p ps=4.06e+07u w=1e+06u l=500000u
+X24 Vref WR a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X25 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X26 Vref WR a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X27 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X28 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X29 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X30 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X31 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X32 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X33 Vref WRb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X34 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X35 row SWref a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X36 a_19432_n4118# WR Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X37 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X38 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X39 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X40 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X41 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X42 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X43 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X44 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X45 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X46 a_19432_n4118# SWref row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X47 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X48 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X49 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X50 Vref WRb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X51 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X52 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X53 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X54 a_13042_n4118# SWrminus row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X55 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X56 row SWref a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X57 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X58 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X59 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X60 row SWrminus a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X61 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X62 a_19432_n4118# SWref row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X63 row SWrminus a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X64 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X65 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X66 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
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+X109 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
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+X117 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
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+X120 a_19432_n4118# SAMPLE Vsample VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X121 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X122 Vrminus Vgnr a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X123 a_19432_n4118# SAMPLE Vsample VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X124 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X125 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X126 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X127 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X128 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X129 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X130 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
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+X132 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X133 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X134 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X135 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X136 a_13042_n4118# Vgnr Vrminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X137 a_13042_n4118# Vgnr Vrminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X138 Vsample SAMPLE a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X139 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X140 Vsample SAMPLE a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X141 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X142 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X143 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X144 a_19432_n4118# SAMPLE Vsample VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X145 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X146 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X147 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X148 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X149 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
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+X153 a_19432_n4118# SAMPLE Vsample VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X154 a_19432_n4118# WR Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
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+X156 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
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+X158 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
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+X161 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
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+X163 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
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+X167 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
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+X170 Vref WR a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
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+X172 Vrminus Vgnr a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X173 a_19432_n4118# SAMPLE Vsample VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X174 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
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+X178 a_19432_n4118# WR Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
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+X183 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X184 Vrminus Vgnr a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X185 a_19432_n4118# WR Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X186 a_13042_n4118# Vgnr Vrminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X187 a_19432_n4118# WR Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+X188 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u
+.ends
+
+.subckt row_driver_big vccd1 Vref WRb Vrminus Vgnr Vgpr LA_B LA_A SEL row SAMPLE Vrplus
++ SAMPLEb decoder2to4_x6_0/Bb decoder2to4_x6_0/A Vsample WR vssd1 vdda1
+Xrow_driver_x30_0 decoder2to4_x6_0/A0 decoder2to4_x6_0/A2 row Vgpr Vrplus Vsample
++ SAMPLEb SAMPLE WR Vref WRb decoder2to4_x6_0/A0b decoder2to4_x6_0/A1b Vgnr Vrminus
++ vdda1 vssd1 row_driver_x30
+Xand_pair_0 SEL LA_A LA_B and_pair_0/OUT_A and_pair_0/OUT_B vssd1 vccd1 and_pair
+Xlevel_up_shifter_drivers_x4_0 and_pair_0/OUT_B decoder2to4_x6_0/B decoder2to4_x6_0/A
++ decoder2to4_x6_0/Ab decoder2to4_x6_0/Bb vccd1 vdda1 and_pair_0/OUT_A vssd1 level_up_shifter_drivers_x4
+Xdecoder2to4_x6_0 decoder2to4_x6_0/B decoder2to4_x6_0/Bb decoder2to4_x6_0/A decoder2to4_x6_0/Ab
++ decoder2to4_x6_0/A1b decoder2to4_x6_0/A2 decoder2to4_x6_0/A0b decoder2to4_x6_0/A0
++ vdda1 vssd1 decoder2to4_x6
+.ends
+
+.subckt row_drivers_16x1 Vref WRb Vrminus A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
++ A13 A14 A15 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 row0 row1 row2
++ row3 row4 row15 row5 row6 row7 row8 row9 row10 row11 row12 row13 row14 SAMPLE SAMPLEb
++ WR Vgpr row_driver_big_15/decoder2to4_x6_0/Bb Vsample row_driver_big_15/decoder2to4_x6_0/A
++ SEL Vgnr vccd1 vssd1 Vrplus vdda1
+Xrow_driver_big_10 vccd1 Vref WRb Vrminus Vgnr Vgpr B10 A10 SEL row10 SAMPLE Vrplus
++ SAMPLEb row_driver_big_10/decoder2to4_x6_0/Bb row_driver_big_10/decoder2to4_x6_0/A
++ Vsample WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_11 vccd1 Vref WRb Vrminus Vgnr Vgpr B11 A11 SEL row11 SAMPLE Vrplus
++ SAMPLEb row_driver_big_11/decoder2to4_x6_0/Bb row_driver_big_11/decoder2to4_x6_0/A
++ Vsample WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_13 vccd1 Vref WRb Vrminus Vgnr Vgpr B13 A13 SEL row13 SAMPLE Vrplus
++ SAMPLEb row_driver_big_13/decoder2to4_x6_0/Bb row_driver_big_13/decoder2to4_x6_0/A
++ Vsample WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_12 vccd1 Vref WRb Vrminus Vgnr Vgpr B12 A12 SEL row12 SAMPLE Vrplus
++ SAMPLEb row_driver_big_12/decoder2to4_x6_0/Bb row_driver_big_12/decoder2to4_x6_0/A
++ Vsample WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_14 vccd1 Vref WRb Vrminus Vgnr Vgpr B14 A14 SEL row14 SAMPLE Vrplus
++ SAMPLEb row_driver_big_14/decoder2to4_x6_0/Bb row_driver_big_14/decoder2to4_x6_0/A
++ Vsample WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_15 vccd1 Vref WRb Vrminus Vgnr Vgpr B15 A15 SEL row15 SAMPLE Vrplus
++ SAMPLEb row_driver_big_15/decoder2to4_x6_0/Bb row_driver_big_15/decoder2to4_x6_0/A
++ Vsample WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_0 vccd1 Vref WRb Vrminus Vgnr Vgpr B0 A0 SEL row0 SAMPLE Vrplus SAMPLEb
++ row_driver_big_0/decoder2to4_x6_0/Bb row_driver_big_0/decoder2to4_x6_0/A Vsample
++ WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_2 vccd1 Vref WRb Vrminus Vgnr Vgpr B2 A2 SEL row2 SAMPLE Vrplus SAMPLEb
++ row_driver_big_2/decoder2to4_x6_0/Bb row_driver_big_2/decoder2to4_x6_0/A Vsample
++ WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_1 vccd1 Vref WRb Vrminus Vgnr Vgpr B1 A1 SEL row1 SAMPLE Vrplus SAMPLEb
++ row_driver_big_1/decoder2to4_x6_0/Bb row_driver_big_1/decoder2to4_x6_0/A Vsample
++ WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_3 vccd1 Vref WRb Vrminus Vgnr Vgpr B3 A3 SEL row3 SAMPLE Vrplus SAMPLEb
++ row_driver_big_3/decoder2to4_x6_0/Bb row_driver_big_3/decoder2to4_x6_0/A Vsample
++ WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_4 vccd1 Vref WRb Vrminus Vgnr Vgpr B4 A4 SEL row4 SAMPLE Vrplus SAMPLEb
++ row_driver_big_4/decoder2to4_x6_0/Bb row_driver_big_4/decoder2to4_x6_0/A Vsample
++ WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_5 vccd1 Vref WRb Vrminus Vgnr Vgpr B5 A5 SEL row5 SAMPLE Vrplus SAMPLEb
++ row_driver_big_5/decoder2to4_x6_0/Bb row_driver_big_5/decoder2to4_x6_0/A Vsample
++ WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_6 vccd1 Vref WRb Vrminus Vgnr Vgpr B6 A6 SEL row6 SAMPLE Vrplus SAMPLEb
++ row_driver_big_6/decoder2to4_x6_0/Bb row_driver_big_6/decoder2to4_x6_0/A Vsample
++ WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_7 vccd1 Vref WRb Vrminus Vgnr Vgpr B7 A7 SEL row7 SAMPLE Vrplus SAMPLEb
++ row_driver_big_7/decoder2to4_x6_0/Bb row_driver_big_7/decoder2to4_x6_0/A Vsample
++ WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_8 vccd1 Vref WRb Vrminus Vgnr Vgpr B8 A8 SEL row8 SAMPLE Vrplus SAMPLEb
++ row_driver_big_8/decoder2to4_x6_0/Bb row_driver_big_8/decoder2to4_x6_0/A Vsample
++ WR vssd1 vdda1 row_driver_big
+Xrow_driver_big_9 vccd1 Vref WRb Vrminus Vgnr Vgpr B9 A9 SEL row9 SAMPLE Vrplus SAMPLEb
++ row_driver_big_9/decoder2to4_x6_0/Bb row_driver_big_9/decoder2to4_x6_0/A Vsample
++ WR vssd1 vdda1 row_driver_big
+.ends
+
+.subckt sky130_fd_sc_hd__buf_4 A VGND VPWR X VNB VPB
+X0 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=8e+11p pd=7.6e+06u as=5.4e+11p ps=5.08e+06u w=1e+06u l=150000u
+X1 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=3.51e+11p pd=3.68e+06u as=5.2e+11p ps=5.5e+06u w=650000u l=150000u
+X5 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X6 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X7 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X8 VPWR A a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=2.6e+11p ps=2.52e+06u w=1e+06u l=150000u
+X9 VGND A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.69e+11p ps=1.82e+06u w=650000u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hd__dfxtp_1 CLK D VGND VPWR Q VNB VPB
+X0 Q a_1059_315# VGND VNB sky130_fd_pr__nfet_01v8 ad=1.69e+11p pd=1.82e+06u as=7.492e+11p ps=8.11e+06u w=650000u l=150000u
+X1 a_891_413# a_193_47# a_634_159# VNB sky130_fd_pr__nfet_01v8 ad=1.368e+11p pd=1.48e+06u as=1.978e+11p ps=1.99e+06u w=360000u l=150000u
+X2 a_561_413# a_27_47# a_466_413# VPB sky130_fd_pr__pfet_01v8_hvt ad=1.533e+11p pd=1.57e+06u as=1.365e+11p ps=1.49e+06u w=420000u l=150000u
+X3 VPWR CLK a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=1.02105e+12p pd=9.61e+06u as=1.664e+11p ps=1.8e+06u w=640000u l=150000u
+X4 Q a_1059_315# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=2.6e+11p pd=2.52e+06u as=0p ps=0u w=1e+06u l=150000u
+X5 a_381_47# D VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=1.155e+11p pd=1.39e+06u as=0p ps=0u w=420000u l=150000u
+X6 VGND a_634_159# a_592_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.392e+11p ps=1.53e+06u w=420000u l=150000u
+X7 VPWR a_891_413# a_1059_315# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=2.7e+11p ps=2.54e+06u w=1e+06u l=150000u
+X8 a_466_413# a_193_47# a_381_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X9 VPWR a_634_159# a_561_413# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 a_634_159# a_466_413# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X11 a_634_159# a_466_413# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=2.19e+11p pd=2.15e+06u as=0p ps=0u w=750000u l=150000u
+X12 a_975_413# a_193_47# a_891_413# VPB sky130_fd_pr__pfet_01v8_hvt ad=1.764e+11p pd=1.68e+06u as=1.134e+11p ps=1.38e+06u w=420000u l=150000u
+X13 VGND a_1059_315# a_1017_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.32e+11p ps=1.49e+06u w=420000u l=150000u
+X14 a_193_47# a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=1.092e+11p pd=1.36e+06u as=0p ps=0u w=420000u l=150000u
+X15 a_891_413# a_27_47# a_634_159# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X16 a_592_47# a_193_47# a_466_413# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.242e+11p ps=1.41e+06u w=360000u l=150000u
+X17 a_1017_47# a_27_47# a_891_413# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=360000u l=150000u
+X18 VPWR a_1059_315# a_975_413# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X19 a_466_413# a_27_47# a_381_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.626e+11p ps=1.66e+06u w=360000u l=150000u
+X20 a_193_47# a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=1.664e+11p pd=1.8e+06u as=0p ps=0u w=640000u l=150000u
+X21 VGND a_891_413# a_1059_315# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.69e+11p ps=1.82e+06u w=650000u l=150000u
+X22 a_381_47# D VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X23 VGND CLK a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.092e+11p ps=1.36e+06u w=420000u l=150000u
+.ends
+
+.subckt comparator inp inm phi1 phi1b latch_high high_buff vssd1 vccd1
+Xsky130_fd_sc_hd__buf_4_0 low vssd1 vccd1 low_buff vssd1 vccd1 sky130_fd_sc_hd__buf_4
+Xsky130_fd_sc_hd__buf_4_1 high vssd1 vccd1 high_buff vssd1 vccd1 sky130_fd_sc_hd__buf_4
+Xsky130_fd_sc_hd__dfxtp_1_0 phi1b low_buff vssd1 vccd1 latch_low vssd1 vccd1 sky130_fd_sc_hd__dfxtp_1
+Xsky130_fd_sc_hd__dfxtp_1_1 phi1b high_buff vssd1 vccd1 latch_high vssd1 vccd1 sky130_fd_sc_hd__dfxtp_1
+X0 FN phi1 vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=1.155e+11p pd=1.39e+06u as=3.997e+12p ps=3.863e+07u w=420000u l=150000u
+X1 pfete FN low vccd1 sky130_fd_pr__pfet_01v8 ad=2.815e+11p pd=2.65e+06u as=2.95e+11p ps=2.59e+06u w=1e+06u l=150000u
+X2 high FP pfetw vccd1 sky130_fd_pr__pfet_01v8 ad=2.95e+11p pd=2.59e+06u as=2.815e+11p ps=2.65e+06u w=1e+06u l=150000u
+X3 FN inm tail vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=1.14e+12p pd=8.57e+06u as=2.28e+12p ps=1.714e+07u w=4e+06u l=500000u
+X4 vccd1 high pfete vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X5 pfetw low vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X6 tail phi1 vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=1.197e+11p pd=1.41e+06u as=3.3007e+12p ps=3.505e+07u w=420000u l=150000u
+X7 vssd1 phi1b high vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.197e+11p ps=1.41e+06u w=420000u l=150000u
+X8 high low vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X9 vccd1 phi1 FP vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=1.155e+11p ps=1.39e+06u w=420000u l=150000u
+X10 FP inp tail vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=1.14e+12p pd=8.57e+06u as=0p ps=0u w=4e+06u l=500000u
+X11 vssd1 phi1b low vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.197e+11p ps=1.41e+06u w=420000u l=150000u
+X12 low high vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt mimcap_stacked m3_n1944_n462# c1_n1752_n412# c2_n1752_n412#
+X0 c2_n1752_n412# c1_n1752_n412# sky130_fd_pr__cap_mim_m3_2 l=5e+06u w=5e+06u
+X1 c1_n1752_n412# m3_n1944_n462# sky130_fd_pr__cap_mim_m3_1 l=5e+06u w=5e+06u
+.ends
+
+.subckt mimcap_stacked_57x50 vssd1 sig
+Xmimcap_stacked_0[0|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[0|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[1|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[2|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[3|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[4|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[5|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[6|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[7|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[8|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[9|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[10|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[11|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[12|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[13|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[14|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[15|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[16|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[17|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[18|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[19|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[20|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[21|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[22|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[23|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[24|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[25|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[26|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[27|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[28|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[29|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[30|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[31|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[32|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[33|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[34|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[35|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[36|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[37|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[38|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[39|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[40|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[41|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[42|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[43|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[44|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[45|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[46|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[47|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[48|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[49|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[50|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[51|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[52|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_0[53|46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[47] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[48] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[49] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[50] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[51] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[52] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_1[53] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[47] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[48] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[49] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[50] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[51] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[52] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_2[53] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[47] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[48] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[49] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[50] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[51] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[52] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_3[53] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[47] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[48] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_4[49] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[47] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[48] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_5[49] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[0] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[1] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[2] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[3] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[4] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[5] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[6] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[7] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[8] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[9] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[10] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[11] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[12] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[13] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[14] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[15] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[16] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[17] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[18] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[19] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[20] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[21] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[22] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[23] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[24] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[25] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[26] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[27] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[28] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[29] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[30] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[31] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[32] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[33] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[34] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[35] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[36] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[37] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[38] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[39] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[40] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[41] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[42] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[43] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[44] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[45] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[46] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[47] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[48] vssd1 sig vssd1 mimcap_stacked
+Xmimcap_stacked_6[49] vssd1 sig vssd1 mimcap_stacked
+.ends
+
+.subckt core A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row_sel latch_high col_sel Vref Vrplus vssd1 Vgpr
+Xcomp_out_sel_0 comparator_0/latch_high latch_high vccd1 row_sel vssd1 comp_out_sel
+X1T1R_16x16_0 1T1R_16x16_0/row2 1T1R_16x16_0/row3 1T1R_16x16_0/row4 1T1R_16x16_0/row5
++ 1T1R_16x16_0/row6 1T1R_16x16_0/row8 1T1R_16x16_0/row9 1T1R_16x16_0/row13 1T1R_16x16_0/row14
++ 1T1R_16x16_0/row15 1T1R_16x16_0/col0 1T1R_16x16_0/col1 1T1R_16x16_0/col2 1T1R_16x16_0/col3
++ 1T1R_16x16_0/col4 1T1R_16x16_0/col5 1T1R_16x16_0/col6 1T1R_16x16_0/col7 1T1R_16x16_0/col8
++ 1T1R_16x16_0/col9 1T1R_16x16_0/col10 1T1R_16x16_0/col11 1T1R_16x16_0/col12 1T1R_16x16_0/col13
++ 1T1R_16x16_0/col14 1T1R_16x16_0/col15 1T1R_16x16_0/WL5 1T1R_16x16_0/WL6 1T1R_16x16_0/WL7
++ 1T1R_16x16_0/WL8 1T1R_16x16_0/WL13 1T1R_16x16_0/WL14 1T1R_16x16_0/row11 1T1R_16x16_0/row10
++ 1T1R_16x16_0/WL2 1T1R_16x16_0/WL4 1T1R_16x16_0/WL15 1T1R_16x16_0/WL3 1T1R_16x16_0/row7
++ 1T1R_16x16_0/WL0 1T1R_16x16_0/WL11 1T1R_16x16_0/WL10 1T1R_16x16_0/WL9 1T1R_16x16_0/row1
++ 1T1R_16x16_0/WL12 1T1R_16x16_0/row12 1T1R_16x16_0/row0 vssd1 1T1R_16x16_0/WL1 x1T1R_16x16
+Xsky130_fd_sc_hd__inv_2_0 phi1b vssd1 vccd1 phi1 vssd1 vccd1 sky130_fd_sc_hd__inv_2
+Xsky130_fd_sc_hd__inv_2_1 RISC_CLK vssd1 vccd1 phi1b vssd1 vccd1 sky130_fd_sc_hd__inv_2
+Xsky130_fd_sc_hd__and2_4_0 row_sel col_sel vssd1 vccd1 SEL vssd1 vccd1 sky130_fd_sc_hd__and2_4
+Xcol_drivers_1x16_0 A0c A15c vdda1 A1c A2c A3c A4c A5c A6c A7c A8c A9c A10c A11c A12c
++ A13c A14c B0c B1c B2c B3c B4c B5c B6c B8c B9c B10c B11c B12c B13c B14c B15c SEL
++ 1T1R_16x16_0/col0 1T1R_16x16_0/col2 1T1R_16x16_0/col3 1T1R_16x16_0/col1 1T1R_16x16_0/col4
++ 1T1R_16x16_0/col5 1T1R_16x16_0/col6 1T1R_16x16_0/col7 1T1R_16x16_0/col8 1T1R_16x16_0/col9
++ 1T1R_16x16_0/col10 1T1R_16x16_0/col11 1T1R_16x16_0/col12 1T1R_16x16_0/col13 1T1R_16x16_0/col14
++ 1T1R_16x16_0/col15 col_drivers_1x16_0/col_driver_big_14/decoder2to4_x6_0/A1b col_drivers_1x16_0/col_driver_big_14/decoder2to4_x6_0/A2
++ col_drivers_1x16_0/col_driver_big_14/decoder2to4_x6_0/A0 Vcminus Vcplus Vref B7c
++ vccd1 vssd1 col_drivers_1x16
+Xsky130_fd_sc_hd__and2_4_1 row_sel col_sel vssd1 vccd1 SEL vssd1 vccd1 sky130_fd_sc_hd__and2_4
+Xsky130_fd_sc_hd__and2_4_2 row_sel col_sel vssd1 vccd1 SEL vssd1 vccd1 sky130_fd_sc_hd__and2_4
+Xand_level_up_shifter_x4_0 SEL vdda1 row_drivers_16x1_0/WRb row_drivers_16x1_0/WR
++ WR vssd1 vccd1 and_level_up_shifter_x4
+Xsky130_fd_sc_hd__and2_4_3 row_sel col_sel vssd1 vccd1 SEL vssd1 vccd1 sky130_fd_sc_hd__and2_4
+Xand_level_up_shifter_x4_1 SEL vdda1 row_drivers_16x1_0/SAMPLEb row_drivers_16x1_0/SAMPLE
++ SAMPLE vssd1 vccd1 and_level_up_shifter_x4
+Xsky130_fd_sc_hd__and2_4_4 row_sel col_sel vssd1 vccd1 SEL vssd1 vccd1 sky130_fd_sc_hd__and2_4
+XWL_drivers_16x1_0 SEL vccd1 vdda1 WL15 WL14 WL13 WL12 WL11 WL10 WL9 WL8 WL7 WL6 WL5
++ WL4 WL3 WL2 WL1 WL0 1T1R_16x16_0/WL15 1T1R_16x16_0/WL14 1T1R_16x16_0/WL13 1T1R_16x16_0/WL12
++ 1T1R_16x16_0/WL11 1T1R_16x16_0/WL10 1T1R_16x16_0/WL9 1T1R_16x16_0/WL8 1T1R_16x16_0/WL7
++ 1T1R_16x16_0/WL6 1T1R_16x16_0/WL5 1T1R_16x16_0/WL4 1T1R_16x16_0/WL3 1T1R_16x16_0/WL2
++ 1T1R_16x16_0/WL1 1T1R_16x16_0/WL0 vssd1 WL_drivers_16x1
+Xrow_drivers_16x1_0 Vref row_drivers_16x1_0/WRb Vrminus A0r A1r A2r A3r A4r A5r A6r
++ A7r A8r A9r A10r A11r A12r A13r A14r A15r B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r
++ B10r B11r B12r B13r B14r B15r 1T1R_16x16_0/row0 1T1R_16x16_0/row1 1T1R_16x16_0/row2
++ 1T1R_16x16_0/row3 1T1R_16x16_0/row4 1T1R_16x16_0/row15 1T1R_16x16_0/row5 1T1R_16x16_0/row6
++ 1T1R_16x16_0/row7 1T1R_16x16_0/row8 1T1R_16x16_0/row9 1T1R_16x16_0/row10 1T1R_16x16_0/row11
++ 1T1R_16x16_0/row12 1T1R_16x16_0/row13 1T1R_16x16_0/row14 row_drivers_16x1_0/SAMPLE
++ row_drivers_16x1_0/SAMPLEb row_drivers_16x1_0/WR Vgpr row_drivers_16x1_0/row_driver_big_15/decoder2to4_x6_0/Bb
++ Vsample row_drivers_16x1_0/row_driver_big_15/decoder2to4_x6_0/A SEL Vgnr vccd1 vssd1
++ Vrplus vdda1 row_drivers_16x1
+Xcomparator_0 Vsample Vref_comp phi1 phi1b comparator_0/latch_high comparator_0/high_buff
++ vssd1 vccd1 comparator
+Xmimcap_stacked_57x50_0 vssd1 Vsample mimcap_stacked_57x50
+.ends
+
+.subckt core_7x6 B0c B2c B6c B7c B9c B10c B11c B12c B14c B15c A0c A1c A12c A14c RISC_CLK
++ SAMPLE A14r A15r Vrminus Vref_comp vdda1 WL5 WL6 WL8 col4_sel row1_sel row2_sel
++ row3_sel row4_sel row5_sel core_interconnect_bottom_left_4/m4_84804_n88270# core_interconnect_bottom_left_15/m4_84084_n88270#
++ core_interconnect_bottom_left_0/m4_84084_n88270# core_interconnect_bottom_left_15/m4_83364_n88270#
++ col2_sel core_interconnect_bottom_left_0/m4_83364_n88270# WR row6_sel core_interconnect_bottom_left_11/m4_84804_n88270#
++ A5c core_interconnect_bottom_left_7/m4_84084_n88270# core_interconnect_bottom_left_12/m4_84084_n88270#
++ core_interconnect_bottom_left_7/m4_83364_n88270# core_interconnect_bottom_left_12/m4_83364_n88270#
++ Vcminus col3_sel core_interconnect_bottom_left_8/m4_84804_n88270# core_interconnect_bottom_left_3/m4_84804_n88270#
++ A15c core_interconnect_bottom_left_4/m4_84084_n88270# A13c core_interconnect_bottom_left_4/m4_83364_n88270#
++ A8c latch_high0 row0_sel B3c A6c B1c A9c col0_sel A7c Vrplus latch_high1 core_interconnect_bottom_left_15/m4_84804_n88270#
++ latch_high2 core_interconnect_bottom_left_0/m4_84804_n88270# col5_sel A2c core_interconnect_bottom_left_11/m4_84084_n88270#
++ latch_high3 core_interconnect_bottom_left_11/m4_83364_n88270# latch_high5 B13r B5r
++ B8r A4c B0r WL1 latch_high4 core_interconnect_bottom_left_7/m4_84804_n88270# core_interconnect_bottom_left_12/m4_84804_n88270#
++ A11r B12r B9r B15r col1_sel A6r B7r B4c B4r WL11 A1r B2r A10r core_interconnect_bottom_left_8/m4_84084_n88270#
++ WL3 A10c Vgnr A5r core_interconnect_bottom_left_3/m4_84084_n88270# B5c A0r A13r
++ B3r Vcplus B11r Vgpr B13c core_interconnect_bottom_left_8/m4_83364_n88270# A8r WL15
++ B14r WL2 B6r WL13 core_interconnect_bottom_left_3/m4_83364_n88270# A3r A9r WL10
++ B1r A12r A3c WL14 A4r vccd1 WL12 A7r WL9 WL0 B10r Vref A2r vssd1 WL7 A11c B8c WL4
+Xcore_6 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c
++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c
++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r
++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1
++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK
++ Vref_comp row0_sel latch_high2 col2_sel Vref Vrplus vssd1 Vgpr core
+Xcore_39 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row6_sel latch_high3 col3_sel Vref Vrplus vssd1 Vgpr core
+Xcore_28 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row4_sel latch_high1 col1_sel Vref Vrplus vssd1 Vgpr core
+Xcore_17 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row3_sel latch_high2 col2_sel Vref Vrplus vssd1 Vgpr core
+Xcore_29 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row4_sel latch_high2 col2_sel Vref Vrplus vssd1 Vgpr core
+Xcore_7 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c
++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c
++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r
++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1
++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK
++ Vref_comp row0_sel latch_high3 col3_sel Vref Vrplus vssd1 Vgpr core
+Xcore_18 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row3_sel latch_high3 col3_sel Vref Vrplus vssd1 Vgpr core
+Xcore_8 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c
++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c
++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r
++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1
++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK
++ Vref_comp row1_sel latch_high5 col5_sel Vref Vrplus vssd1 Vgpr core
+Xcore_19 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row2_sel latch_high3 col3_sel Vref Vrplus vssd1 Vgpr core
+Xcore_9 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c
++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c
++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r
++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1
++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK
++ Vref_comp row1_sel latch_high4 col4_sel Vref Vrplus vssd1 Vgpr core
+Xcore_40 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row6_sel latch_high4 col4_sel Vref Vrplus vssd1 Vgpr core
+Xcore_41 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row6_sel latch_high5 col5_sel Vref Vrplus vssd1 Vgpr core
+Xcore_30 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row4_sel latch_high3 col3_sel Vref Vrplus vssd1 Vgpr core
+Xcore_31 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row5_sel latch_high3 col3_sel Vref Vrplus vssd1 Vgpr core
+Xcore_20 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row2_sel latch_high4 col4_sel Vref Vrplus vssd1 Vgpr core
+Xcore_32 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row5_sel latch_high4 col4_sel Vref Vrplus vssd1 Vgpr core
+Xcore_10 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row0_sel latch_high4 col4_sel Vref Vrplus vssd1 Vgpr core
+Xcore_21 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row3_sel latch_high4 col4_sel Vref Vrplus vssd1 Vgpr core
+Xcore_0 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c
++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c
++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r
++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1
++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK
++ Vref_comp row0_sel latch_high0 col0_sel Vref Vrplus vssd1 Vgpr core
+Xcore_33 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row5_sel latch_high5 col5_sel Vref Vrplus vssd1 Vgpr core
+Xcore_11 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row0_sel latch_high5 col5_sel Vref Vrplus vssd1 Vgpr core
+Xcore_22 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row2_sel latch_high5 col5_sel Vref Vrplus vssd1 Vgpr core
+Xcore_1 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c
++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c
++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r
++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1
++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK
++ Vref_comp row0_sel latch_high1 col1_sel Vref Vrplus vssd1 Vgpr core
+Xcore_34 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row4_sel latch_high5 col5_sel Vref Vrplus vssd1 Vgpr core
+Xcore_12 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row3_sel latch_high0 col0_sel Vref Vrplus vssd1 Vgpr core
+Xcore_23 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row3_sel latch_high5 col5_sel Vref Vrplus vssd1 Vgpr core
+Xcore_2 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c
++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c
++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r
++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1
++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK
++ Vref_comp row1_sel latch_high1 col1_sel Vref Vrplus vssd1 Vgpr core
+Xcore_35 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row4_sel latch_high4 col4_sel Vref Vrplus vssd1 Vgpr core
+Xcore_13 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row2_sel latch_high0 col0_sel Vref Vrplus vssd1 Vgpr core
+Xcore_24 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row4_sel latch_high0 col0_sel Vref Vrplus vssd1 Vgpr core
+Xcore_3 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c
++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c
++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r
++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1
++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK
++ Vref_comp row1_sel latch_high0 col0_sel Vref Vrplus vssd1 Vgpr core
+Xcore_36 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row6_sel latch_high0 col0_sel Vref Vrplus vssd1 Vgpr core
+Xcore_25 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row5_sel latch_high0 col0_sel Vref Vrplus vssd1 Vgpr core
+Xcore_14 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row2_sel latch_high1 col1_sel Vref Vrplus vssd1 Vgpr core
+Xcore_4 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c
++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c
++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r
++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1
++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK
++ Vref_comp row1_sel latch_high3 col3_sel Vref Vrplus vssd1 Vgpr core
+Xcore_37 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row6_sel latch_high1 col1_sel Vref Vrplus vssd1 Vgpr core
+Xcore_26 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row5_sel latch_high1 col1_sel Vref Vrplus vssd1 Vgpr core
+Xcore_15 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row3_sel latch_high1 col1_sel Vref Vrplus vssd1 Vgpr core
+Xcore_38 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row6_sel latch_high2 col2_sel Vref Vrplus vssd1 Vgpr core
+Xcore_27 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row5_sel latch_high2 col2_sel Vref Vrplus vssd1 Vgpr core
+Xcore_5 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c
++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c
++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r
++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1
++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK
++ Vref_comp row1_sel latch_high2 col2_sel Vref Vrplus vssd1 Vgpr core
+Xcore_16 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c
++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c
++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r
++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r
++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c
++ B4c RISC_CLK Vref_comp row2_sel latch_high2 col2_sel Vref Vrplus vssd1 Vgpr core
+.ends
+
+.subckt top Vgnr Vrminus vccd1 vdda1 RSEL2 RSEL1 RSEL0 cA0 cA1 cA2 cA3 cA4 cA5 cA6
++ cA7 cA8 cA9 cA10 cA11 cA12 cA13 cA14 cA15 cB0 cB1 cB2 cB3 cB4 cB5 cB6 cB7 cB8 cB9
++ cB10 cB11 cB12 cB13 cB14 cB15 rA0 rA1 rA2 rA3 rA4 rA5 rA6 rA7 rA8 rA9 rA10 rA11
++ rA12 rA13 rA14 rA15 rB0 rB1 rB2 rB3 rB4 rB5 rB6 rB7 rB8 rB9 rB10 rB11 rB12 rB13
++ rB14 rB15 WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15
++ WR SAMPLE RISC_CLK CSEL2 CSEL1 CSEL0 Vref_comp EN latch_high4 latch_high0 latch_high1
++ latch_high2 latch_high3 latch_high5 Vrplus Vgpr Vref Vcplus Vcminus vssa1
+Xtop_interconnect_0 WL4 core_7x6_0/col5_sel cA2 latch_high5 core_7x6_0/row6_sel WL3
++ latch_high4 cA3 vccd1 WL2 cA4 latch_high3 vssa1 core_7x6_0/col2_sel rB0 Vref WL1
++ vssa1 cA5 latch_high2 core_7x6_0/row3_sel rB1 WL0 cA6 latch_high1 WR SAMPLE rB2
++ cA7 latch_high0 rB3 cA8 cA10 vssa1 core_7x6_0/row0_sel rB4 cA9 cA11 rB5 vdda1 cA12
++ rB6 cA13 rB7 cA14 vccd1 Vrplus vdda1 rB8 Vcminus cA15 rB9 Vref RISC_CLK vdda1 core_7x6_0/col3_sel
++ core_7x6_0/row4_sel rB10 RSEL1 rB11 RSEL0 core_7x6_0/col0_sel vssa1 rB12 core_7x6_0/row1_sel
++ cB0 rB13 vccd1 cB1 Vref rB14 rA0 RSEL2 cB2 rB15 rA1 cB3 Vref_comp vccd1 rA2 vdda1
++ cB4 Vref rA3 vccd1 cB5 rA4 vssa1 vssa1 CSEL1 cB6 vssa1 rA5 vccd1 cB7 CSEL0 core_7x6_0/col4_sel
++ WL15 rA6 Vcplus core_7x6_0/row5_sel cB8 WL14 rA7 Vgnr EN cB9 WL13 rA10 rA8 vdda1
++ core_7x6_0/col1_sel WL12 rA11 rA9 Vgpr Vref vssa1 core_7x6_0/row2_sel WL11 rA12
++ cB10 WL10 rA13 Vref vdda1 vssa1 WL9 rA14 cB11 vccd1 vdda1 vssa1 WL8 cB12 rA15 vdda1
++ vccd1 Vref Vref vccd1 WL7 cB13 Vrminus WL6 cB14 cA0 CSEL2 WL5 cB15 cA1 vssa1 vdda1
++ vdda1 Vref top_interconnect
+Xcore_7x6_0 cB0 cB2 cB6 cB7 cB9 cB10 cB11 cB12 cB14 cB15 cA0 cA1 cA12 cA14 RISC_CLK
++ SAMPLE rA14 rA15 Vrminus Vref_comp vdda1 WL5 WL6 WL8 core_7x6_0/col4_sel core_7x6_0/row1_sel
++ core_7x6_0/row2_sel core_7x6_0/row3_sel core_7x6_0/row4_sel core_7x6_0/row5_sel
++ vdda1 Vref Vref vccd1 core_7x6_0/col2_sel vccd1 WR core_7x6_0/row6_sel vdda1 cA5
++ Vref Vref vccd1 vccd1 Vcminus core_7x6_0/col3_sel vdda1 vdda1 cA15 Vref cA13 vccd1
++ cA8 latch_high0 core_7x6_0/row0_sel cB3 cA6 cB1 cA9 core_7x6_0/col0_sel cA7 Vrplus
++ latch_high1 vdda1 latch_high2 vdda1 core_7x6_0/col5_sel cA2 Vref latch_high3 vccd1
++ latch_high5 rB13 rB5 rB8 cA4 rB0 WL1 latch_high4 vdda1 vdda1 rA11 rB12 rB9 rB15
++ core_7x6_0/col1_sel rA6 rB7 cB4 rB4 WL11 rA1 rB2 rA10 Vref WL3 cA10 Vgnr rA5 Vref
++ cB5 rA0 rA13 rB3 Vcplus rB11 Vgpr cB13 vccd1 rA8 WL15 rB14 WL2 rB6 WL13 vccd1 rA3
++ rA9 WL10 rB1 rA12 cA3 WL14 rA4 vccd1 WL12 rA7 WL9 WL0 rB10 Vref rA2 vssa1 WL7 cA11
++ cB8 WL4 core_7x6
.ends
.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
+ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
+ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
-+ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
-+ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
-+ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
+ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
-+ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[7] io_analog[8] io_analog[9]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[7] io_analog[8] io_analog[9] io_analog[4]
+ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
-+ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
-+ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
-+ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
-+ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
-+ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
-+ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
-+ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
-+ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
-+ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
-+ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
-+ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
-+ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
-+ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
-+ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
-+ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
-+ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
-+ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
-+ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
-+ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
-+ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
-+ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
-+ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
-+ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
-+ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
-+ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
-+ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
-+ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
-+ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
-+ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
-+ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
-+ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ io_clamp_low[1] io_clamp_low[2] vssa1 io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16]
++ io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24]
++ io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8]
++ io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12] io_in_3v3[13] io_in_3v3[14]
++ io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18] io_in_3v3[19] io_in_3v3[1]
++ io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23] io_in_3v3[24] io_in_3v3[25]
++ io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4] io_in_3v3[5] io_in_3v3[6] io_in_3v3[7]
++ io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13]
++ io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20]
++ io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[2] io_oeb[3]
++ io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8] io_oeb[9] io_out[0] io_out[10]
++ io_out[11] io_out[12] io_out[13] io_out[14] io_out[15] io_out[16] io_out[17] io_out[18]
++ io_out[19] io_out[1] io_out[20] io_out[21] io_out[22] io_out[23] io_out[24] io_out[25]
++ io_out[26] io_out[2] io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8]
++ io_out[9] la_data_in[0] la_data_in[100] la_data_in[101] la_data_in[102] la_data_in[103]
++ la_data_in[104] la_data_in[105] la_data_in[106] la_data_in[107] la_data_in[108]
++ la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111] la_data_in[112] la_data_in[113]
++ la_data_in[114] la_data_in[115] la_data_in[116] la_data_in[117] la_data_in[118]
++ la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121] la_data_in[122] la_data_in[123]
++ la_data_in[124] la_data_in[125] la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13]
++ la_data_in[14] la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19]
++ la_data_in[1] la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24]
++ la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2]
++ la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35]
++ la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40]
++ la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46]
++ la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51]
++ la_data_in[52] la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57]
++ la_data_in[58] la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62]
++ la_data_in[63] la_data_in[64] la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68]
++ la_data_in[69] la_data_in[6] la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73]
++ la_data_in[74] la_data_in[75] la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79]
++ la_data_in[7] la_data_in[80] la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84]
++ la_data_in[85] la_data_in[86] la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8]
++ la_data_in[90] la_data_in[91] la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95]
++ la_data_in[96] la_data_in[97] la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0]
++ la_data_out[100] la_data_out[101] la_data_out[102] la_data_out[103] la_data_out[104]
++ la_data_out[105] la_data_out[106] la_data_out[107] la_data_out[108] la_data_out[109]
++ la_data_out[10] la_data_out[110] la_data_out[111] la_data_out[112] la_data_out[113]
++ la_data_out[114] la_data_out[115] la_data_out[116] la_data_out[117] la_data_out[118]
++ la_data_out[119] la_data_out[11] la_data_out[120] la_data_out[121] la_data_out[122]
++ la_data_out[123] la_data_out[124] la_data_out[125] la_data_out[126] la_data_out[127]
++ la_data_out[12] la_data_out[13] la_data_out[14] la_data_out[15] la_data_out[16]
++ la_data_out[17] la_data_out[18] la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21]
++ la_data_out[22] la_data_out[23] la_data_out[24] la_data_out[25] la_data_out[26]
++ la_data_out[27] la_data_out[28] la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31]
++ la_data_out[32] la_data_out[33] la_data_out[34] la_data_out[35] la_data_out[36]
++ la_data_out[37] la_data_out[38] la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41]
++ la_data_out[42] la_data_out[43] la_data_out[44] la_data_out[45] la_data_out[46]
++ la_data_out[47] la_data_out[48] la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51]
++ la_data_out[52] la_data_out[53] la_data_out[54] la_data_out[55] la_data_out[56]
++ la_data_out[57] la_data_out[58] la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61]
++ la_data_out[62] la_data_out[63] la_data_out[64] la_data_out[65] la_data_out[66]
++ la_data_out[67] la_data_out[68] la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71]
++ la_data_out[72] la_data_out[73] la_data_out[74] la_data_out[75] la_data_out[76]
++ la_data_out[77] la_data_out[78] la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81]
++ la_data_out[82] la_data_out[83] la_data_out[84] la_data_out[85] la_data_out[86]
++ la_data_out[87] la_data_out[88] la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91]
++ la_data_out[92] la_data_out[93] la_data_out[94] la_data_out[95] la_data_out[96]
++ la_data_out[97] la_data_out[98] la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100]
++ la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107]
++ la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113]
++ la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11]
++ la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126]
++ la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17]
++ la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23]
++ la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2]
++ la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36]
++ la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42]
++ la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49]
++ la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55]
++ la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61]
++ la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68]
++ la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74]
++ la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80]
++ la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87]
++ la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93]
++ la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9]
++ user_clock2 user_irq[0] user_irq[1] user_irq[2] vccd1 vccd2 vdda1 vdda2 vssd1 vssd2 vssa2
++ wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12]
++ wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18]
++ wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23]
++ wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29]
++ wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5]
++ wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10]
++ wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15] wbs_dat_i[16]
++ wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1] wbs_dat_i[20] wbs_dat_i[21]
++ wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26] wbs_dat_i[27]
++ wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30] wbs_dat_i[31] wbs_dat_i[3]
++ wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9] wbs_dat_o[0]
++ wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14] wbs_dat_o[15]
++ wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1] wbs_dat_o[20]
++ wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25] wbs_dat_o[26]
++ wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30] wbs_dat_o[31]
++ wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9]
++ wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
+Xtop_0 gpio_analog[2] gpio_noesd[3] vccd1 io_clamp_high[2] la_data_in[118] la_data_in[119]
++ la_data_in[120] la_data_in[0] la_data_in[1] la_data_in[2] la_data_in[3] la_data_in[4]
++ la_data_in[5] la_data_in[6] la_data_in[7] la_data_in[8] la_data_in[9] la_data_in[10]
++ la_data_in[11] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[20] la_data_in[21] la_data_in[22]
++ la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28]
++ la_data_in[29] la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34]
++ la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[40]
++ la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46]
++ la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[50] la_data_in[51] la_data_in[52]
++ la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58]
++ la_data_in[59] la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64]
++ la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[70]
+ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
-+ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
-+ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
-+ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
-+ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
-+ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
-+ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
-+ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
-+ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
-+ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
-+ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
-+ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
-+ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
-+ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
-+ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
-+ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
-+ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
-+ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
-+ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
-+ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
-+ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
-+ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
-+ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
-+ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
-+ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
-+ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
-+ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
-+ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
-+ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
-+ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
-+ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
-+ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
-+ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
-+ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
-+ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
-+ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
-+ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
-+ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
-+ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
-+ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
-+ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
-+ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
-+ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
-+ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
-+ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
-+ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
-+ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
-+ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
-+ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
-+ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
-+ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
-+ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
-+ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
-+ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
-+ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
-+ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
-+ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
-+ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
-+ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
-+ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
-+ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
-+ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
-+ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
-+ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
-+ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
-+ wbs_stb_i wbs_we_i
-Xuser_analog_proj_example_0 io_out[16] io_out[12] vdda1 io_out[11] io_analog[4] gpio_analog[3]
-+ io_out[15] gpio_analog[7] vssa1 vccd1 vccd1 user_analog_proj_example
-R0 vssa1 io_clamp_low[2] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R1 io_oeb[15] vssd1 sky130_fd_pr__res_generic_m3 w=560000u l=600000u
-R2 io_analog[4] io_clamp_high[0] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R3 vssd1 io_oeb[11] sky130_fd_pr__res_generic_m3 w=560000u l=580000u
-R4 vssa1 io_clamp_low[1] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R5 io_oeb[16] vssd1 sky130_fd_pr__res_generic_m3 w=560000u l=310000u
-R6 vssa1 io_clamp_low[0] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R7 vssd1 io_oeb[12] sky130_fd_pr__res_generic_m3 w=560000u l=490000u
-R8 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R9 vssa1 io_clamp_high[1] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[80] la_data_in[81] la_data_in[82]
++ la_data_in[103] la_data_in[104] la_data_in[105] gpio_analog[17] la_data_in[112]
++ la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98]
++ la_data_out[97] gpio_noesd[6] gpio_analog[16] gpio_noesd[0] io_analog[4] gpio_noesd[5]
++ vssa1 top
.ends
diff --git a/verilog/rtl/.reram_crossbar.v.swp b/verilog/rtl/.reram_crossbar.v.swp
new file mode 100644
index 0000000..ff077ee
--- /dev/null
+++ b/verilog/rtl/.reram_crossbar.v.swp
Binary files differ
diff --git a/verilog/rtl/.user_analog_project_wrapper.v.swp b/verilog/rtl/.user_analog_project_wrapper.v.swp
new file mode 100644
index 0000000..49de1cf
--- /dev/null
+++ b/verilog/rtl/.user_analog_project_wrapper.v.swp
Binary files differ
diff --git a/verilog/rtl/reram_crossbar.v b/verilog/rtl/reram_crossbar.v
new file mode 100755
index 0000000..f9a0c7f
--- /dev/null
+++ b/verilog/rtl/reram_crossbar.v
@@ -0,0 +1,369 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+/*
+ * I/O mapping for analog
+ *
+ * mprj_io[37] io_in/out/oeb/in_3v3[26] --- ---
+ * mprj_io[36] io_in/out/oeb/in_3v3[25] --- ---
+ * mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] ---
+ * mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] ---
+ * mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] ---
+ * mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] ---
+ * mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] ---
+ * mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] ---
+ * mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] ---
+ * mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] ---
+ * mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] ---
+ * mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] ---
+ * mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] ---
+ * mprj_io[24] --- --- user_analog[10]
+ * mprj_io[23] --- --- user_analog[9]
+ * mprj_io[22] --- --- user_analog[8]
+ * mprj_io[21] --- --- user_analog[7]
+ * mprj_io[20] --- --- user_analog[6] clamp[2]
+ * mprj_io[19] --- --- user_analog[5] clamp[1]
+ * mprj_io[18] --- --- user_analog[4] clamp[0]
+ * mprj_io[17] --- --- user_analog[3]
+ * mprj_io[16] --- --- user_analog[2]
+ * mprj_io[15] --- --- user_analog[1]
+ * mprj_io[14] --- --- user_analog[0]
+ * mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] ---
+ * mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] ---
+ * mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] ---
+ * mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] ---
+ * mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] ---
+ * mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] ---
+ * mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] ---
+ * mprj_io[6] io_in/out/oeb/in_3v3[6] --- ---
+ * mprj_io[5] io_in/out/oeb/in_3v3[5] --- ---
+ * mprj_io[4] io_in/out/oeb/in_3v3[4] --- ---
+ * mprj_io[3] io_in/out/oeb/in_3v3[3] --- ---
+ * mprj_io[2] io_in/out/oeb/in_3v3[2] --- ---
+ * mprj_io[1] io_in/out/oeb/in_3v3[1] --- ---
+ * mprj_io[0] io_in/out/oeb/in_3v3[0] --- ---
+ *
+ */
+
+/*
+ *----------------------------------------------------------------
+ *
+ * user_analog_proj_example
+ *
+ * This is an example of a (trivially simple) analog user project,
+ * showing how the user project can connect to the I/O pads, both
+ * the digital pads, the analog connection on the digital pads,
+ * and the dedicated analog pins used as an additional power supply
+ * input, with a connected ESD clamp.
+ *
+ * See the testbench in directory "mprj_por" for the example
+ * program that drives this user project.
+ *
+ *----------------------------------------------------------------
+ */
+
+module reram_crossbar (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ // GPIO-analog
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ // Dedicated analog
+ inout [`ANALOG_PADS-1:0] io_analog,
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Clock
+ input user_clock2,
+
+ // IRQ
+ output [2:0] irq
+);
+ //wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
+ //wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
+ //wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
+ //wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
+ wire [`ANALOG_PADS-1:0] io_analog;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd;
+ wire [127:0] la_data_in;
+ wire [127:0] la_data_out;
+
+ // wire [31:0] rdata;
+ // wire [31:0] wdata;
+
+ // wire valid;
+ // wire [3:0] wstrb;
+
+ //wire isupply; // Independent 3.3V supply
+ wire vdd3v3, vdd1v8, vss;
+ //wire io16, io15, io12, io11;
+ wire Vcplus, Vcminus, Vref, Vrplus, Vrminus, Vgpr, Vgnr, Vref_comp;
+ wire WR, SAMPLE, RISC_CLK, RSEL0, RSEL1, RSEL2, CSEL0, CSEL1, CSEL2, EN;
+ wire latch_high0, latch_high1, latch_high2, latch_high3, latch_high4, latch_high5;
+ wire cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7, cA8, cA9, cA10, cA11, cA12, cA13, cA14, cA15,
+ cB0, cB1, cB2, cB3, cB4, cB5, cB6, cB7, cB8, cB9, cB10, cB11, cB12, cB13, cB14, cB15,
+ rB0, rB1, rB2, rB3, rB4, rB5, rB6, rB7, rB8, rB9, rB10, rB11, rB12, rB13, rB14, rB15,
+ rA0, rA1, rA2, rA3, rA4, rA5, rA6, rA7, rA8, rA9, rA10, rA11, rA12, rA13, rA14, rA15,
+ WL0, WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8, WL9, WL10, WL11, WL12, WL13, WL14, WL15;
+
+ // WB MI A
+ // assign valid = wbs_cyc_i && wbs_stb_i;
+ // assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+ // assign wbs_dat_o = rdata;
+ // assign wdata = wbs_dat_i;
+
+ // IO --- unused (no need to connect to anything)
+ // assign io_out[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = 0;
+ // assign io_out[14:13] = 11'b0;
+ // assign io_out[10:0] = 11'b0;
+
+ // assign io_oeb[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = -1;
+ // assign io_oeb[14:13] = 11'b1;
+ // assign io_oeb[10:0] = 11'b1;
+
+ // IO --- enable outputs on 11, 12, 15, and 16
+ //assign io_out[12:11] = {io12, io11};
+ //assign io_oeb[12:11] = {vssd1, vssd1};
+
+ //assign io_out[16:15] = {io16, io15};
+ //assign io_oeb[16:15] = {vssd1, vssd1};
+
+ assign Vcplus = gpio_noesd[1];
+ assign gpio_noesd[14] = Vcplus;
+ assign io_analog[4] = Vcplus;
+
+ assign Vcminus = gpio_noesd[5];
+ assign gpio_noesd[7] = Vcminus;
+ assign io_analog[5] = Vcminus;
+
+ assign Vref = gpio_noesd[0];
+ assign gpio_noesd[8] = Vref;
+ assign io_analog[6] = Vref;
+
+ assign Vrplus = gpio_noesd[6];
+ assign gpio_noesd[9] = Vrplus;
+
+ assign Vrminus = gpio_noesd[3];
+ assign gpio_noesd[10] = Vrminus;
+
+ assign Vgpr = gpio_analog[16];
+
+ assign Vgnr = gpio_analog[2];
+
+ assign Vref_comp = gpio_analog[17];
+
+ assign cA0 = la_data_in[0]; // LA input
+ assign cA1 = la_data_in[1]; // LA input
+ assign cA2 = la_data_in[2]; // LA input
+ assign cA3 = la_data_in[3]; // LA input
+ assign cA4 = la_data_in[4]; // LA input
+ assign cA5 = la_data_in[5]; // LA input
+ assign cA6 = la_data_in[6]; // LA input
+ assign cA7 = la_data_in[7]; // LA input
+ assign cA8 = la_data_in[8]; // LA input
+ assign cA9 = la_data_in[9]; // LA input
+ assign cA10 = la_data_in[10]; // LA input
+ assign cA11 = la_data_in[11]; // LA input
+ assign cA12 = la_data_in[12]; // LA input
+ assign cA13 = la_data_in[13]; // LA input
+ assign cA14 = la_data_in[14]; // LA input
+ assign cA15 = la_data_in[15]; // LA input
+
+ assign cB0 = la_data_in[16]; // LA input
+ assign cB1 = la_data_in[17]; // LA input
+ assign cB2 = la_data_in[18]; // LA input
+ assign cB3 = la_data_in[19]; // LA input
+ assign cB4 = la_data_in[20]; // LA input
+ assign cB5 = la_data_in[21]; // LA input
+ assign cB6 = la_data_in[22]; // LA input
+ assign cB7 = la_data_in[23]; // LA input
+ assign cB8 = la_data_in[24]; // LA input
+ assign cB9 = la_data_in[25]; // LA input
+ assign cB10 = la_data_in[26]; // LA input
+ assign cB11 = la_data_in[27]; // LA input
+ assign cB12 = la_data_in[28]; // LA input
+ assign cB13 = la_data_in[29]; // LA input
+ assign cB14 = la_data_in[30]; // LA input
+ assign cB15 = la_data_in[31]; // LA input
+
+ assign rA0 = la_data_in[32]; // LA input
+ assign rA1 = la_data_in[33]; // LA input
+ assign rA2 = la_data_in[34]; // LA input
+ assign rA3 = la_data_in[35]; // LA input
+ assign rA4 = la_data_in[36]; // LA input
+ assign rA5 = la_data_in[37]; // LA input
+ assign rA6 = la_data_in[38]; // LA input
+ assign rA7 = la_data_in[39]; // LA input
+ assign rA8 = la_data_in[40]; // LA input
+ assign rA9 = la_data_in[41]; // LA input
+ assign rA10 = la_data_in[42]; // LA input
+ assign rA11 = la_data_in[43]; // LA input
+ assign rA12 = la_data_in[44]; // LA input
+ assign rA13 = la_data_in[45]; // LA input
+ assign rA14 = la_data_in[46]; // LA input
+ assign rA15 = la_data_in[47]; // LA input
+
+ assign rB0 = la_data_in[48]; // LA input
+ assign rB1 = la_data_in[49]; // LA input
+ assign rB2 = la_data_in[50]; // LA input
+ assign rB3 = la_data_in[51]; // LA input
+ assign rB4 = la_data_in[52]; // LA input
+ assign rB5 = la_data_in[53]; // LA input
+ assign rB6 = la_data_in[54]; // LA input
+ assign rB7 = la_data_in[55]; // LA input
+ assign rB8 = la_data_in[56]; // LA input
+ assign rB9 = la_data_in[57]; // LA input
+ assign rB10 = la_data_in[58]; // LA input
+ assign rB11 = la_data_in[59]; // LA input
+ assign rB12 = la_data_in[60]; // LA input
+ assign rB13 = la_data_in[61]; // LA input
+ assign rB14 = la_data_in[62]; // LA input
+ assign rB15 = la_data_in[63]; // LA input
+
+ assign WL0 = la_data_in[64]; // LA input
+ assign WL1 = la_data_in[65]; // LA input
+ assign WL2 = la_data_in[66]; // LA input
+ assign WL3 = la_data_in[67]; // LA input
+ assign WL4 = la_data_in[68]; // LA input
+ assign WL5 = la_data_in[69]; // LA input
+ assign WL6 = la_data_in[70]; // LA input
+ assign WL7 = la_data_in[71]; // LA input
+ assign WL8 = la_data_in[72]; // LA input
+ assign WL9 = la_data_in[73]; // LA input
+ assign WL10 = la_data_in[74]; // LA input
+ assign WL11 = la_data_in[75]; // LA input
+ assign WL12 = la_data_in[76]; // LA input
+ assign WL13 = la_data_in[77]; // LA input
+ assign WL14 = la_data_in[78]; // LA input
+ assign WL15 = la_data_in[79]; // LA input
+
+ assign WR = la_data_in[80]; // LA input
+ assign SAMPLE = la_data_in[81]; // LA input
+ assign RISC_CLK = la_data_in[82]; // LA input
+
+ assign la_data_out[97] = latch_high5; // LA output
+ assign la_data_out[98] = latch_high3; // LA output
+ assign la_data_out[99] = latch_high2; // LA output
+ assign la_data_out[100] = latch_high1; // LA output
+ assign la_data_out[101] = latch_high0; // LA output
+ assign la_data_out[102] = latch_high4; // LA output
+
+ assign CSEL2 = la_data_in[103]; // LA input
+ assign CSEL1 = la_data_in[104]; // LA input
+ assign CSEL0 = la_data_in[105]; // LA input
+ assign EN = la_data_in[112]; // LA input
+ assign RSEL2 = la_data_in[118]; // LA input
+ assign RSEL1 = la_data_in[119]; // LA input
+ assign RSEL0 = la_data_in[120]; // LA input
+
+
+ // IRQ
+ assign irq = 3'b000; // Unused
+
+ // LA --- unused (no need to connect to anything)
+ // assign la_data_out = {128{1'b0}}; // Unused
+
+ // Instantiate the POR. Connect the digital power to user area 1
+ // VCCD, and connect the analog power to user area 1 VDDA.
+
+ // Monitor the 3.3V output with mprj_io[10] = gpio_analog[3]
+ // Monitor the 1.8V outputs with mprj_io[11,12] = io_out[11,12]
+
+ //example_por por1 (
+ // `ifdef USE_POWER_PINS
+ // .vdd3v3(vdda1),
+ // .vdd1v8(vccd1),
+ // .vss(vssa1),
+ // `endif
+ // .porb_h(gpio_analog[3]), // 3.3V domain output
+ // .porb_l(io11), // 1.8V domain output
+ // .por_l(io12) // 1.8V domain output
+ //);
+
+ // Instantiate 2nd POR with the analog power supply on one of the
+ // analog pins. NOTE: io_analog[4] = mproj_io[18] and is the same
+ // pad with io_clamp_high/low[0].
+
+ `ifdef USE_POWER_PINS
+ assign vdd3v3 = vdda1;
+ assign vdda2 = vdd3v3;
+
+ assign vdd1v8 = vccd1;
+ assign vccd2 = vdd1v8;
+
+ assign vss = vssa1;
+ assign vssa2 = vss;
+
+ //assign io_clamp_high[0] = isupply;
+ //assign io_clamp_low[0] = vssa1;
+
+ // Tie off remaining clamps
+ assign io_clamp_high[2:0] = vdd3v3;
+ assign io_clamp_low[2:0] = vss;
+ `endif
+
+ // Monitor the 3.3V output with mprj_io[25] = gpio_analog[7]
+ // Monitor the 1.8V outputs with mprj_io[26,27] = io_out[15,16]
+
+ //example_por por2 (
+ // `ifdef USE_POWER_PINS
+ // .vdd3v3(isupply),
+ // .vdd1v8(vccd1),
+ // .vss(vssa1),
+ // `endif
+ // .porb_h(gpio_analog[7]), // 3.3V domain output
+ // .porb_l(io15), // 1.8V domain output
+ // .por_l(io16) // 1.8V domain output
+ //);
+
+endmodule
+
+`default_nettype wire
diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v
index 7a73f76..4f9ea1c 100644
--- a/verilog/rtl/user_analog_project_wrapper.v
+++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -123,7 +123,7 @@
/* User project is instantiated here */
/*--------------------------------------*/
-user_analog_proj_example mprj (
+reram_crossbar crossbar1 (
`ifdef USE_POWER_PINS
.vdda1(vdda1), // User area 1 3.3V power
.vdda2(vdda2), // User area 2 3.3V power
