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foss-eda-tools / third_party / shuttle / sky130 / mpw-008 / slot-008 / ef49b899fcbca822167ebc3bfabf9ab1791f4ad0
commitef49b899fcbca822167ebc3bfabf9ab1791f4ad0[log] [tgz]
authorStaf Verhaegen <staf@fibraservi.eu>Tue Mar 22 09:16:27 2022 +0100
committerStaf Verhaegen <staf@fibraservi.eu>Tue Mar 22 09:16:27 2022 +0100
treea90e0e648cd642a5274bc9b2930c4809f2b9871d
parent590196545153e363e62b5d860078fa4c398ab8ad [diff]
Another try to fix XOR errors
2 files changed
tree: a90e0e648cd642a5274bc9b2930c4809f2b9871d
  1. .github/
  2. docs/
  3. doitcode/
  4. gds/
  5. netgen/
  6. verilog/
  7. xschem/
  8. caravel
  9. .gitignore
  10. dodo.py
  11. LICENSE
  12. Makefile
  13. README.md
  14. user_analog_project_wrapper.png
README.md

PDKMaster based memory compiler test chip

TBD

Source

The top level is fully generated from python code in the doitcode subdirectory. pydoit is used to generate the desig with the provided dodo.py file in the top directory. The code depends on some external modules that are assumed to be installed:

  • PDKMaster: python framework (under heavy development) to ease generation of circuits and corresponding DRC compliant layout. This based on a description of a technology with python souce code to allow easy porting to different technologies.
  • c4m-flexcell: a (currently minimal) standard cell library based on PDKMaster
  • c4m-flexmem: the source for the memory compiler
  • c4m-pdk-sky130: the source for the PDKMaster based PDK for the Sky130 technology.

License

The resulting GDS files is released under the LGPL 2.1 or later license. Some of the source code to generate the GDS is under the GPL 2.0 or later license.